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| 8127f?avr?02/2013 features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture ? 54 powerful instructions ? most single clock cycle execution ? 16 x 8 general purpose working registers ? fully static operation ? up to 12 mips throughput at 12 mhz ? non-volatile program and data memories ? 512/1024 bytes of in-system programmable flash program memory ? 32 bytes internal sram ? flash write/erase cycles: 10,000 ? data retention: 20 years at 85 o c / 100 years at 25 o c ? peripheral features ?qtouch ? library support for capacitive touch sensing (1 channel) ? one 16-bit timer/counter with prescaler and two pwm channels ? programmable watchdog timer with separate on-chip oscillator ? 4-channel, 8-bit analog to digital converter (attiny5/10, only) ? on-chip analog comparator ? special microcontroller features ? in-system programmable (at 5v, only) ? external and internal interrupt sources ? low power idle, adc noise reduction, and power-down modes ? enhanced power-on reset circuit ? programmable supply voltage level monitor with interrupt and reset ? internal calibrated oscillator ? i/o and packages ? four programmable i/o lines ? 6-pin sot and 8-pad udfn ? operating voltage: ? 1.8 ? 5.5v ? programming voltage: ?5v ? speed grade ? 0 ? 4 mhz @ 1.8 ? 5.5v ? 0 ? 8 mhz @ 2.7 ? 5.5v ? 0 ? 12 mhz @ 4.5 ? 5.5v ? industrial and extended temperature ranges ? low power consumption ? active mode: ? 200a at 1mhz and 1.8v ? idle mode: ? 25a at 1mhz and 1.8v ? power-down mode: ? < 0.1a at 1.8v atmel 8-bit avr microcontroller with 512/1024 bytes in-system programmable flash attiny4 / attiny5 / attiny9 / attiny10 rev. 8127f?avr?02/2013
2 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 1. pin configurations figure 1-1. pinout of attiny4/5/9/10 1.1 pin description 1.1.1 vcc supply voltage. 1.1.2 gnd ground. 1.1.3 port b (pb3..pb0) this is a 4-bit, bi-directional i/o port with internal pull-up resistors, indi vidually selectable for each bit. the output buffers have symmetrical drive characteri stics, with both high sink and source capability. as inputs, the port pins that are externally pulled low will source current if pull- up resistors are activated. port pins are tri-stated when a reset condition becomes active, even if the clock is not running. the port also serves the functions of various special features of th e attiny4/5/9/10, as listed on page 36 . 1.1.4 reset reset input. a low le vel on this pin for longer than the minimum pulse le ngth will generate a reset, even if the clock is not running and provided the reset pin has not bee n disabled. the minimum pulse length is given in table 16-4 on page 118 . shorter pulses are not guaranteed to generate a reset. the reset pin can also be used as a (weak) i/o pin. 1 2 3 6 5 4 (pcint0/tpidata/oc0a/adc0/ain0) pb0 gnd (pcint1/tpiclk/clki/icp0/oc0b/adc1/ain1) pb1 pb3 (reset/pcint3/adc3) vcc pb2 (t0/clko/pcint2/int0/adc2) sot-23 1 2 3 4 8 7 6 5 (pcint1/tpiclk/clki/icp0/oc0b/adc1/ain1) pb1 nc nc gnd pb2 (t0/clko/pcint2/int0/adc2) vcc pb3 (reset/pcint3/adc3) pb0 (ain0/adc0/oc0a/tpidata/pcint0) udfn 3 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 2. overview attiny4/5/9/10 are low-power cmos 8-bit microcontrol lers based on the compact avr enhanced risc architec- ture. by executing powerful instructions in a singl e clock cycle, the attiny4/5/9/10 achieve throughputs approaching 1 mips per mhz, allowing the system designer to optimize po wer consumption versus processing speed. figure 2-1. block diagram the avr core combines a rich instruct ion set with 16 general purpose workin g registers and system registers. all registers are directly connected to the arithmetic logic unit (alu), a llowing two independent registers to be accessed in one single instruction executed in one clock cyc le. the resulting architecture is compact and code effi- cient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. the attiny4/5/9/10 provide the following features: 512/1024 byte of in-system programmable flash, 32 bytes of sram, four general purpose i/o lines, 16 general purpose wo rking registers, a 16-bit timer/counter with two pwm stack pointer sram program counter programming logic isp interface internal oscillator watchdog timer reset flag register mcu status register timer/ counter0 calibrated oscillator timing and control interrupt unit analog comparator adc general purpose registers x y z alu status register program flash instruction register instruction decoder control lines v cc reset data register port b direction reg. port b drivers port b gnd pb3:0 8-bit data bus 4 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 channels, internal and ex ternal interrupts, a pr ogrammable wa tchdog timer with internal oscillator, an internal cali- brated oscillator, and four software selectable power saving modes. attiny5/10 are also equipped with a four- channel, 8-bit analog to digital converter (adc). idle mode stops the cpu while allowing the sram, timer/counter, adc (attiny5/10, only), analog comparator, and interrupt system to continue functi oning. adc noise reduction mode minimizes switchi ng noise during adc con- versions by stopping the cpu and all i/o modules except the adc. in power-down mode registers keep their contents and all chip functions are disabled until the next interrupt or hard ware reset. in stan dby mode, the oscilla- tor is running while the rest of the device is sleeping, allowing very fast start-up combined with low power consumption. the device is manufactured using atmel?s high density non- volatile memory technology. the on-chip, in-system programmable flash allows program memory to be re -programmed in-system by a conventional, non-volatile memory programmer. the attiny4/5/9/10 avr are supported by a suite of program and system development tools, including macro assemblers and evaluation kits. 2.1 comparison of attiny4, at tiny5, attiny9 and attiny10 a comparison of the devices is shown in table 2-1 . table 2-1. differences between attiny4, attiny5, attiny9 and attiny10 device flash adc signature attiny4 512 bytes no 0x1e 0x8f 0x0a attiny5 512 bytes yes 0x1e 0x8f 0x09 attiny9 1024 bytes no 0x1e 0x90 0x08 attiny10 1024 bytes yes 0x1e 0x90 0x03 5 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 3. general information 3.1 resources a comprehensive set of drivers, application notes, data s heets and descriptions on dev elopment tools are available for download at http://www.atmel.com /microcontroller/avr . 3.2 code examples this documentation contains simple co de examples that briefly show how to use various parts of the device. these code examples assume that the part specific header file is included before compilation. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compile r documentation for more details. 3.3 capacitive touch sensing atmel qtouch library provides a simple to use solution for touch sensitive interfac es on atmel avr microcon- trollers. the qtouch library includes support for qtouch ? and qmatrix ? acquisition methods. touch sensing is easily added to any application by linki ng the qtouch library and using the application program- ming interface (api) of the library to define the touch channels and sensors. the applicati on then calls the api to retrieve channel information and determine the state of the touch sensor. the qtouch library is free and can be downloaded from the atmel website. for more information and details of implementation, refer to the qtouch library user guide ? also available from the atmel website. 3.4 data retention reliability qualification results show that the projected data retention failure ra te is much less than 1 ppm over 20 years at 85c or 100 years at 25c. 6 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 4. cpu core this section discusses the avr core ar chitecture in general. the main function of the cpu core is to ensure cor- rect program execution. the cpu mu st therefore be able to access memo ries, perform calculations, control peripherals, and handle interrupts. 4.1 architectural overview figure 4-1. block diagram of the avr architecture in order to maximize performance and parallelism, the avr uses a harvard architecture ? with separate memories and buses for program and data. instructions in the program memory are executed with a single level pipelining. while one instruction is being executed , the next instruction is pre-fetched from the program memory. this concept enables instructions to be executed in every clock cy cle. the program memory is in-system reprogrammable flash memory. the fast-access register file contai ns 16 x 8-bit general purpose work ing registers with a single clock cycle access time. this allows singl e-cycle arithmetic logic unit (alu) operation. in a typi cal alu operation, two oper- ands are output from the register file, the operation is ex ecuted, and the result is stored back in the register file ? in one clock cycle. flash program memory instruction register instruction decoder program counter control lines 16 x 8 general purpose registrers alu status and con trol i/o lines data bus 8-bit data sra m direct addressing indirect addressing interrupt unit watchdog timer analog comparator timer/counter 0 adc 7 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 six of the 16 registers can be used as three 16-bit indire ct address register pointers for data space addressing ? enabling efficient address calculations. one of the these address pointers can also be used as an address pointer for look up tables in flash program memory. these added f unction registers are the 16-bit x-, y-, and z-register, described later in this section. the alu supports arithmetic and logi c operations between registers or bet ween a constant and a register. single register operations can also be executed in the alu. afte r an arithmetic operation, t he status regist er is updated to reflect information about the result of the operation. program flow is provided by conditional and unconditional jump and call instructions, capable of directly addressing the whole address space. most avr instructions have a sing le 16-bit word format but 32-bit wide instructions also exist. the actual instruction set va ries, as some devices only implem ent a part of the instruction set. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectively allocated in the general data sram, and cons equently the stack size is only limited by the sram size and the usage of the sram. all user programs must initialize the sp in the reset routine (before subroutines or interrupts are executed). the stack pointer (sp) is read/write accessible in the i/o space. the data sram can easily be accessed through the four different ad dressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its contro l registers in the i/o space with an additional global interrupt enable bit in the status register. all interrupts have a separate in terrupt vector in the interrupt vector table. the interrupts have priority in accordance with their interrupt vector positio n. the lower the interrupt vector address, the higher the priority. the i/o memory space contains 64 addresses for cpu peripheral functions as control registers, spi, and other i/o functions. the i/o memory can be accessed as the data space locations, 0x0000 - 0x003f. 4.2 alu ? arithm etic logic unit the high-performance avr alu operates in direct connection with all the 16 general purpose working registers. within a single clock cycle, arithmetic operations between general purpose re gisters or between a register and an immediate are executed. the alu operat ions are divided into three main cat egories ? arithmetic, logical, and bit- functions. some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and frac tional format. see document ?avr instruction set? and section ?instruction set summary? on page 150 for a detailed description. 4.3 status register the status register contains information about the result of the most re cently executed arithmetic instruction. this information can be used for altering program flow in order to perform conditional operations. note that the status register is updated after all alu operations, as spec ified in document ?avr inst ruction set? and section ?instruc- tion set summary? on page 150 . this will in many cases remove the need for using the dedicated compare instructions, resulting in fa ster and more compact code. the status register is not automatically stored when entering an inte rrupt routine and restored when returning from an interrupt. this must be handled by software. 4.4 general purpose register file the register file is optimized for the avr enhanced risc instruction set. in order to achieve the required perfor- mance and flexibility, the followin g input/output scheme s are supported by the register file: ? one 8-bit output operand and one 8-bit result input ? two 8-bit output operands and one 8-bit result input ? one 16-bit output operand and one 16-bit result input 8 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 4-2 below shows the structure of the 16 gene ral purpose working registers in the cpu. figure 4-2. avr cpu general purpose working registers note: a typical implementation of the avr register file incl udes 32 general prupose registers but attiny4/5/9/10 implement only 16 registers. for reasons of compatibility the r egisters are numbered r16...r31, not r0...r15. most of the instructions oper ating on the register file have direct access to all registers, and most of them are sin- gle cycle instructions. 4.4.1 the x-register, y-register, and z-register registers r26..r31 have some added functions to their general purpose usage. these registers are 16-bit address pointers for indirect addressing of the data space. the three indirect address registers x, y, and z are defined as described in figure 4-3 . figure 4-3. the x-, y-, and z-registers 70 r16 r17 general r18 purpose ? working r26 x-register low byte registers r27 x-register high byte r28 y-register low byte r29 y-register high byte r30 z-register low byte r31 z-register high byte 15 xh xl 0 x-register 707 0 r27 r26 15 yh yl 0 y-register 707 0 r29 r28 15 zh zl 0 z-register 707 0 r31 r30 9 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 in different addressing modes these address registers f unction as automatic increment and automatic decrement (see document ?avr instruction set? and section ?instruction set summary? on page 150 for details). 4.5 stack pointer the stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. the stack pointer register alwa ys points to the top of th e stack. note that the stack is implemented as growing from higher memory loca tions to lower memory loca tions. this implies that a stack push command decr eases the stack pointer. the stack pointer points to the data sram stack area where the subroutine and interrupt stacks are located. this stack space in the data sram must be defined by the pr ogram before any subroutine calls are executed or inter- rupts are enabled. the stack pointer must be set to poi nt above 0x40. the stack po inter is decremented by one when data is pushed onto the stack with the push instru ction, and it is decremented by two when the return address is pushed onto the stack with s ubroutine call or interrupt. the stack pointer is incremented by one when data is popped from the stack with the pop instruction, an d it is incremented by two when data is popped from the stack with return from subroutine re t or return from interrupt reti. the avr stack pointer is implemented as two 8-bit registers in the i/o space. the number of bits actually used is implementation dependent. note that the data space in so me implementations of the avr architecture is so small that only spl is needed. in this case , the sph register will not be present. 4.6 instruction execution timing this section describes the general acce ss timing concepts for instruction exec ution. the avr cpu is driven by the cpu clock clk cpu , directly generated from the selected clock source for the chip. no internal clock division is used. figure 4-4. the parallel instruction fetches and instruction executions figure 4-4 shows the parallel instruction fetches and instruct ion executions enabled by the harvard architecture and the fast access register file concept. this is the ba sic pipelining concept to obtain up to 1 mips per mhz with the correspondin g unique results for functions per cost, functions per clocks, and functions per power-unit. figure 4-5 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register operands is executed, and the result is stored back to the destination register. clk 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 cpu 10 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 4-5. single cycle alu operation 4.7 reset and in terrupt handling the avr provides several different interrupt sources. thes e interrupts and the separate reset vector each have a separate program vector in the program memory space. all interrupts are assigned i ndividual enable bits which must be written logic one together with the global interrupt enable bit in the status register in order to enable the interrupt. the lowest addresses in the program memory space are by default defined as the reset and interrupt vectors. the complete list of vectors is shown in ?interrupts? on page 35 . the list also determines the priority levels of the different interrupts. the lower the address the hi gher is the priority level. reset has the highest priority, and next is int0 ? the external interrupt request 0. when an interrupt occurs, the global interrupt enable i-bit is cleared and all interrupts are disabled. the user soft- ware can write logic one to the i-bit to enable nested inte rrupts. all enabled interrupts can then interrupt the current interrupt routine. the i-bit is automatically set when a return from interrupt instruction ? reti ? is executed. there are basically two types of interrupts. the first type is triggered by an event that sets the interrupt flag. for these interrupts, the program counter is vectored to the ac tual interrupt vector in order to execute the interrupt handling routine, and hardware clears the corresponding inte rrupt flag. interrupt flags can also be cleared by writ- ing a logic one to the flag bit position(s) to be cleared. if an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be se t and remembered un til the interrupt is enabled, or the flag is cleared by software. similarly, if one or more interrupt conditions occu r while the global interrupt enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the glo bal interrupt enable bit is set, and will then be executed by order of priority. the second type of interrupts will trigger as long as the interrupt condition is present. these inte rrupts do not nec- essarily have interrupt flags. if the interrupt condition disappears before the interrupt is ena bled, the interrupt will not be triggered. when the avr exits from an inte rrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. note that the status regist er is not automatically stored when enteri ng an interrupt routine, nor restored when returning from an interrupt routine. this must be handled by software. when using the cli instruction to disabl e interrupts, the in terrupts will be immediately disabled. no interrupt will be executed after the cli instruction, even if it occurs simultaneously with the cli instruction. total execution time register operands fetch alu operation execute result write back t1 t2 t3 t4 clk cpu 11 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 when using the sei instruction to enabl e interrupts, the instruct ion following sei will be ex ecuted before any pend- ing interrupts, as shown in the following example. note: see ?code examples? on page 5 . 4.7.1 interrupt response time the interrupt execution response for all the enabled avr inte rrupts is four clock cycles minimum. after four clock cycles the program vector address for the actual interrupt handling routine is executed. during this four clock cycle period, the program counter is pushed onto the stack. the vector is norma lly a jump to the interrupt routine, and this jump takes three clock cycles. if an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. if an interrup t occurs when the mcu is in sleep mode, the interrupt exe- cution response time is increased by four clock cycles. this increase comes in addition to the start-up time from the selected sleep mode. a return from an interrupt handling routine takes four clock cycles. during these four clock cycles, the program counter (two bytes) is popped back from the stack, the st ack pointer is incremented by two, and the i-bit in sreg is set. 4.8 register description 4.8.1 ccp ? configuration change protection register ? bits 7:0 ? ccp[7:0] ? configuration change protection in order to change the contents of a prot ected i/o register the ccp register mu st first be written with the correct signature. after ccp is written the pr otected i/o registers may be written to during the next four cpu instruction cycles. all interrupts are ignored during these cycles. afte r these cycles interrupts are automatically handled again by the cpu, and any pending interrupts will be executed according to their priority. when the protected i/o register signature is written, ccp[0] will read as one as long as the protected feature is enabled, while ccp[7:1] will always read as zero. table 4-1 shows the signatures that are in recognised. assembly code example sei ; set global interrupt enable sleep ; enter sleep, waiting for interrupt ; note: will enter sleep before any pending interrupt(s) bit 76543210 0x3c ccp[7:0] ccp read/write wwwwwwwr/w initial value00000000 table 4-1. signatures recognised by the confi guration change protection register signature group description 0xd8 ioreg: clkmsr, clkpsr, wdtcsr protected i/o register 12 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 4.8.2 sph and spl ? stack pointer register 4.8.3 sreg ? status register ? bit 7 ? i: global interrupt enable the global interrupt enable bit must be set for the interrup ts to be enabled. the individual interrupt enable control is then performed in separate control registers. if the glob al interrupt enable register is cleared, none of the inter- rupts are enabled independent of the individual interrupt e nable settings. the i-bit is cleared by hardware after an interrupt has occurred, and is set by the reti instruction to enable subsequent interrupts. the i-bit can also be set and cleared by the application with the sei and cli instruct ions, as described in the document ?avr instruction set? and ?instruction set summary? on page 150 . ? bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (bit st ore) use the t-bit as source or destination for the oper- ated bit. a bit from a register in the register file can be copied into t by the bst inst ruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. ? bit 5 ? h: half carry flag the half carry flag h indicates a half carry in some arithmetic operations. ha lf carry is useful in bcd arithmetic. see document ?avr instruction set? and section ?instruction set summary? on page 150 for detailed information. ? bit 4 ? s: sign bit, s = n ?? v the s-bit is always an exclusive or between the negative flag n and the two?s comple ment overflow flag v. see document ?avr instruct ion set? and section ?instruction set summary? on page 150 for detailed information. ? bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag v supports two?s complement arithmetic s. see document ?avr instruction set? and section ?instruction set summary? on page 150 for detailed information. ? bit 2 ? n: negative flag the negative flag n indicates a negative result in an arithmetic or logic operation. see document ?avr instruction set? and section ?instruction set summary? on page 150 for detailed information. ? bit 1 ? z: zero flag the zero flag z indicates a zero result in an arithmetic or logic operation. see document ?avr instruction set? and section ?instruction set summary? on page 150 for detailed information. bit 151413121110 9 8 0x3e sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sph 0x3d sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value ramend ramend ramend ramend ramend ramend ramend ramend initial value ramend ramend ramend ramend ramend ramend ramend ramend bit 76543210 0x3f i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 13 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 ? bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetic or logic operation. see document ?avr instruction set? and section ?instruction set summary? on page 150 for detailed information. 14 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 5. memories this section describes the different memories in the at tiny4/5/9/10. devices have tw o main memory areas, the program memory space and the data memory space. 5.1 in-system re-programma ble flash program memory the attiny4/5/9/10 contain 51 2/1024 bytes of on-chip, in-system reprogrammable flash memory for program stor- age. since all avr instructions are 16 or 32 bi ts wide, the flash is organized as 256/512 x 16. the flash memory has an endurance of at least 10,000 wr ite/erase cycles. the atti ny4/5/9/10 program counter (pc) is 9 bits wide, thus capable of addressing the 256/512 program memory locations, starting at 0x000. ?memory programming? on page 106 contains a detailed description on flash data serial downloading. constant tables can be allocated within the entire addre ss space of program memory . since program memory can not be accessed directly, it has been mapped to the data memory. the mapped program memory begins at byte address 0x4000 in data memory (see figure 5-1 on page 15 ). although programs are executed starting from address 0x000 in program memory it must be addressed starting from 0x4000 when accessed via the data memory. internal write operations to flash program memory have been disabled and program memory therefore appears to firmware as read-only. flash memory can still be written to externally but internal write operations to the program memory area will not be succesful. timing diagrams of instruction fetc h and execution are presented in ?instruction execution timing? on page 9 . 5.2 data memory data memory locations include the i/o memory, the internal sram memory, the non-volatile memory lock bits, and the flash memory. see figure 5-1 on page 15 for an illustration on how the attiny4/5/9/10 memory space is organized. the first 64 locations are reserved for i/o memory, while the following 32 data memory locations address the inter- nal data sram. the non-volatile memory lock bits and all the flash memory sections are mapped to the data memory space. these locations appear as read-only for device firmware. the four different addressing modes for data memory are direct, indirect, indirect with pre-decrement, and indirect with post-increment. in the register file, registers r26 to r 31 function as pointer registers for indirect addressing. the in and out instructions can access all 64 locations of i/o memory. direct addressing using the lds and sts instructions reaches the 128 loca tions between 0x0040 and 0x00bf. the indirect addressing reaches the entire data memory space. when using indirect addressing modes with auto- matic pre-decrement and post-increment, the address re gisters x, y, and z are decremented or incremented. 15 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 5-1. data memory map (byte addressing) 5.2.1 data memory access times this section describes the general acce ss timing concepts for internal memo ry access. the internal data sram access is performed in two clk cpu cycles as described in figure 5-2 . figure 5-2. on-chip data sram access cycles 0x0000 ... 0x003f 0x0040 ... 0x005f 0x0060 ... 0x3eff 0x3f00 ... 0x3f01 0x3f02 ... 0x3f3f 0x3f40 ... 0x3f41 0x3f42 ... 0x3f7f 0x3f80 ... 0x3f81 0x3f82 ... 0x3fbf 0x3fc0 ... 0x3fc3 0x3fc4 ... 0x3fff 0x4000 ... 0x41ff/0x43ff 0x4400 ... 0xffff i/o space sram data memory (reserved) nvm lock bits (reserved) configuration bits (reserved) calibration bits (reserved) device id bits (reserved) flash program memory (reserved) clk wr rd data data address address valid t1 t2 t3 compute address read write cpu memory access instruction next instruction 16 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 5.3 i/o memory the i/o space definition of the attiny4/5/9/10 is shown in ?register summary? on page 148 . all attiny4/5/9/10 i/os and peripherals are placed in th e i/o space. all i/o locations may be accessed using the ld and st instructions, enabling data transfer between t he 16 general purpose working registers and the i/o space. i/o registers within the address range 0x00 - 0x1f are dire ctly bit-accessible using th e sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. see document ?avr instruction set? and section ?instruction set summary? on page 150 for more details. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. for compatibility with future devices, reserved bits sh ould be written to zero if accessed. reserved i/o memory addresses should never be written. some of the status flags are cleared by writing a logical one to them. note that cbi and sbi instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. the cbi and sbi instructions work on registers in t he address range 0x00 to 0x1f, only. the i/o and peripherals control registers are explained in later sections. 17 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 6. clock system figure 6-1 presents the principal clock systems and their distri bution in attiny4/5/9/10. all of the clocks need not be active at a given time. in order to reduce power co nsumption, the clocks to m odules not being used can be halted by using different sleep modes and powe r reduction register bits, as described in ?power management and sleep modes? on page 23 . the clock systems is detailed below. figure 6-1. clock distribution 6.1 clock subsystems the clock subsystems are deta iled in the sections below. 6.1.1 cpu clock ? clk cpu the cpu clock is routed to parts of the system concerned with operation of the avr core. examples of such mod- ules are the general purpose register file, the syst em registers and the sram data memory. halting the cpu clock inhibits the core from performi ng general operations and calculations. 6.1.2 i/o clock ? clk i/o the i/o clock is used by the majority of the i/o modules, like timer/counter. the i/o clock is also used by the external interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the i/o clock is halted. 6.1.3 nvm clock - clk nvm the nvm clock controls operat ion of the non-volatile memo ry controller. the nvm clock is usually active simulta- neously with the cpu clock. clock control unit general i/o modules analog-to-digital converter cpu core watchdog timer reset logic clock prescaler ram clock switch nvm calibrated oscillator clk adc source clock clk i/o clk cpu clk nvm watchdog clock watchdog oscillator external clock 18 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 6.1.4 adc clock ? clk adc the adc is provided with a dedicated clock domain. this a llows halting the cpu and i/o clocks in order to reduce noise generated by digital circuitry. this gives more accurate adc conversion results. the adc is available in attiny5/10, only. 6.2 clock sources all synchronous clock signals are derived from the main cl ock. the device has three alternative sources for the main clock, as follows: ? calibrated internal 8 mhz oscillator (see page 18 ) ? external clock (see page 18 ) ? internal 128 khz oscillator (see page 19 ) see table 6-3 on page 21 on how to select and change the active clock source. 6.2.1 calibrated intern al 8 mhz oscillator the calibrated internal oscillator provides an appr oximately 8 mhz clock signal. though voltage and temperature dependent, this clock can be very accurately calibrated by the user. see table 16-2 on page 117 , figure 17-39 on page 141 and figure 17-40 on page 141 for more details. this clock may be selected as the main clock by settin g the clock main select bits clkms[1:0] in clkmsr to 0b00. once enabled, the osc illator will operate with no external componen ts. during reset, hardware loads the cal- ibration byte into the osccal register and thereby automatically calibrates the os cillator. the accuracy of this calibration is shown as factory calibration in table 16-2 on page 117 . when this oscillator is used as th e main clock, the watchdo g oscillator will still be used for the watchdog timer and reset time-out. for more information on the pre-programmed calibration value, see section ?calibration section? on page 109 . 6.2.2 external clock to use the device with an external clock s ource, clki should be driven as shown in figure 6-2 . the external clock is selected as the main clock by sett ing clkms[1:0] bits in clkmsr to 0b10. figure 6-2. external clock drive configuration when applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the mcu. a variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. it is required to ensure that the mc u is kept in reset during such changes in the clock frequency. external clock s ignal clki gnd 19 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 6.2.3 internal 128 khz oscillator the internal 128 khz oscillator is a low power oscill ator providing a clock of 128 khz. the frequency depends on supply voltage, temperature and batch vari ations. this clock may be select as the main clock by setting the clkms[1:0] bits in clkmsr to 0b01. 6.2.4 switching clock source the main clock source can be switched at run-time using the ?clkmsr ? clock main se ttings register? on page 21 . when switching between any clock s ources, the clock system ensures that no glitch occurs in the main clock. 6.2.5 default clock source the calibrated internal 8 mhz oscillator is always sele cted as main clock when the device is powered up or has been reset. the synchronous system clock is the main cloc k divided by 8, controlled by the system clock pres- caler. the clock prescaler select bits can be written later to change the system clock frequency. see ?system clock prescaler?. 6.3 system clock prescaler the system clock is derived from the main clock via th e system clock prescaler. the system clock can be divided by setting the ?clkpsr ? clock prescale register? on page 22 . the system clock prescaler can be used to decrease power consumption at times when requirements for processing power is low or to bring the system clock within limits of maximum frequ ency. the prescaler can be used with all ma in clock source opti ons, and it will affect the clock frequency of the cpu and all synchronous peripherals. the system clock prescaler can be used to implement run- time changes of the internal clock frequency while still ensuring stable operation. 6.3.1 switching prescaler setting when switching between prescaler settings, the system cloc k prescaler ensures that no glitch occurs in the system clock and that no intermediate frequency is higher than neither the clock frequency corresponding the previous set- ting, nor the clock frequency corresponding to the new setting. the ripple counter that implements the prescaler runs at th e frequency of the main cloc k, which may be faster than the cpu's clock frequency. hence, it is not possible to determine t he state of the prescaler - even if it were read- able, and the exact time it takes to switch from one clock division to another cannot be exactly predicted. from the time the clkps values are written, it takes between t1 + t2 and t1 + 2*t2 before the new clock fre- quency is active. in this interval, two active clock edges are produced. here, t1 is the previous clock period, and t2 is the period corresponding to the new prescaler setting. 20 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 6.4 starting 6.4.1 starting from reset the internal reset is immediately asserted when a reset sour ce goes active. the internal reset is kept asserted until the reset source is released and the start-up sequence is completed. the start-up sequence includes three steps, as follows. 1. the first step after the reset source has been released consists of the device counting the reset start-up time. the purpose of this reset start-up time is to en sure that supply voltage has reached sufficient levels. the reset start-up time is counted usin g the internal 128 khz oscillator. see table 6-1 for details of reset start-up time. note that the actual supply voltage is not monitored by th e start-up logic. the device will count until the reset start-up time has elapsed even if the device ha s reached sufficient supply voltage levels earlier. 2. the second step is to count the os cillator start-up time, which ensures th at the calibrated internal oscillator has reached a stable state before it is used by the other parts of the system. the calibrated internal oscil- lator needs to oscillate for a mi nimum number of cycles before it can be co nsidered stable. see table 6-1 for details of the osc illator start-up time. 3. the last step before releasing the internal reset is to load the calibration and the configuration values from the non-volatile memory to configure the device properly. the configuration time is listed in table 6-1 . notes: 1. after powering up the device or after a reset the system clock is automatically set to calibrated internal 8 mhz oscil- lator, divided by 8 6.4.2 starting from power-down mode when waking up from power-down sleep mode, the supply voltage is assumed to be at a sufficient level and only the oscillator start-up time is counted to ensure th e stable operation of the oscillato r. the oscillator start-up time is counted on the selected main clock, and the start-up time depends on the clock selected. see table 6-2 for details. notes: 1. the start-up time is measur ed in main clock oscillator cycles. 6.4.3 starting from idle / adc noise reduction / standby mode when waking up from idle, adc noise reduction or standby mode, the oscillato r is already running and no oscilla- tor start-up time is introduced. the adc is available in attiny5/10, only. table 6-1. start-up times when using the in ternal calibrated oscillator reset oscillator configuration total start-up time 64 ms 6 cycles 21 cycles 64 ms + 6 oscilla tor cycles + 21 system clock cycles (1) table 6-2. start-up time from power-down sleep mode. oscillator start-up time total start-up time 6 cycles 6 oscillator cycles (1) 21 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 6.5 register description 6.5.1 clkmsr ? clock main settings register ? bit 7:2 ? res: reserved bits these bits are reserved and always read zero. ? bit 1:0 ? clkms[1:0]: clock main select bits these bits select the main clock source of the system. t he bits can be written at run-time to switch the source of the main clock. the clock system ensures glit ch free switching of the main clock source. the main clock alternatives are shown in table 6-3 . to avoid unintentional swit ching of main clock source, a protec ted change sequence must be followed to change the clkms bits, as follows: 1. write the signature for change enable of protected i/o register to register ccp 2. within four instruction cycles, write the clkms bits with the desired value 6.5.2 osccal ? oscillato r calibration register . ? bits 7:0 ? cal[7:0]: oscillator calibration value the oscillator calibration register is used to trim the calibrated internal oscillator and remove process variations from the oscillator frequency. a pre-programmed calibration value is automatically written to this register during chip reset, giving the factory ca librated frequency as specified in table 16-2, ?calibration accuracy of internal rc oscillator,? on page 117 . the application software can write this register to change the oscillator frequency. the os cillator can be calibrated to frequencies as specified in table 16-2, ?calibration accuracy of internal rc oscillator,? on page 117 . calibration outside the range given is not guaranteed. the cal[7:0] bits are used to tune t he frequency of the os cillator. a setting of 0x00 gi ves the lowest frequency, and a setting of 0xff gives the highest frequency. bit 765432 1 0 0x37 ? ? ? ? ? ? clkms1 clkms0 clkmsr read/write r r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 6-3. selection of main clock clkm1 clkm0 main clock source 0 0 calibrated internal 8 mhzoscillator 0 1 internal 128 khz oscillator (wdt oscillator) 1 0 external clock 11reserved bit 76543210 0x39 cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 osccal read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x 22 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 6.5.3 clkpsr ? clock prescale register ? bits 7:4 ? res: reserved bits these bits are reserved and will always read as zero. ? bits 3:0 ? clkps[3:0]: clock prescaler select bits 3 - 0 these bits define the division factor between the selected clock source and the internal system clock. these bits can be written at run-time to vary the clock frequency and suit the application requir ements. as the prescaler divides the master clock input to the mcu, the speed of all synchronous peripherals is reduced accordingly. the division factors are given in table 6-4 . to avoid unintentional changes of clock frequency, a pr otected change sequence must be followed to change the clkps bits: 1. write the signature for change enable of protected i/o register to register ccp 2. within four instruct ion cycles, write the desired value to clkps bits at start-up, clkps bits ar e reset to 0b0011 to select the clock division fa ctor of 8. if the sele cted clock source has a frequency higher than the maximum allowed the applicatio n software must make sure a sufficient division factor is used. to make sure the write procedure is not interrup ted, interrupts must be disabl ed when changing prescaler settings. bit 76543210 0x36 ? ? ? ? clkps3 clkps2 clkps1 clkps0 clkpsr read/write r r r r r/w r/w r/w r/w initial value00000011 table 6-4. clock prescaler select clkps3 clkps2 clkps1 clkps0 clock division factor 0000 1 0001 2 0010 4 0011 8 (default) 0100 16 0101 32 0110 64 0111 128 1000 256 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved 23 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 7. power management and sleep modes the high performance and industry leadi ng code efficiency makes the avr microcontrollers an ideal choise for low power applications. in addition, sleep modes enable the application to shut down unused modules in the mcu, thereby saving power. the avr provides various sleep modes allowing the user to tailor the power consumption to the application?s requirements. 7.1 sleep modes figure 6-1 on page 17 presents the different clock systems and thei r distribution in attiny4/5/9/10. the figure is helpful in selecting an appropriate sleep mode. table 7-1 shows the different sleep modes and their wake up sources. note: 1. the adc is available in attiny5/10, only 2. for int0, only level interrupt. to enter any of the four sleep modes, the se bits in smcr must be written to logic one and a sleep instruction must be executed. the sm2: 0 bits in the smcr register select wh ich sleep mode (idle, adc noise reduction, standby or power-down) will be acti vated by the sleep instruction. see table 7-2 for a summary. if an enabled interrupt occurs while the mcu is in a sl eep mode, the mcu wakes up. the mcu is then halted for four cycles in addition to the start- up time, executes the interrupt routine, and resumes execution from the instruc- tion following sleep. the contents of the register file and sram are unaltered when the device wakes up from sleep. if a reset occurs during sleep mode, the m cu wakes up and executes from the reset vector. note that if a level triggere d interrupt is used for wake-up the changed level must be held for some time to wake up the mcu (and for the mcu to enter the interrupt service routine). see ?external interrupts? on page 36 for details. 7.1.1 idle mode when bits sm2:0 are written to 000, the sleep instruct ion makes the mcu en ter idle mode, stopping the cpu but allowing the analog comparator, timer/counter, watchdog, and the interrupt system to continue operating. this sleep mode basically halts clk cpu and clk nvm , while allowing the other clocks to run. idle mode enables the mcu to wake up from external trigge red interrupts as well as internal ones like the timer overflow. if wake-up from the analog comparator interrup t is not required, the analog comparator can be powered down by setting the acd bit in ?acsr ? analog comparator control and status register? on page 80 . this will reduce power consumption in idle mode. if the adc is enab led (attiny5/10, only), a conversion starts automatically when this mode is entered. table 7-1. active clock domains and wake-up so urces in different sleep modes sleep mode active clock domains oscillators wake-up sources clk cpu clk nvm clk io clk adc (1) main clock source enabled int0 and pin change adc (1) other i/o watchdog interrupt vlm interrupt idle xx x xxxxx adc noise reduction x x x (2) xxx standby x x (2) x power-down x (2) x 24 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 7.1.2 adc noise reduction mode when bits sm2:0 are written to 001, the sleep inst ruction makes the mcu enter adc noise reduction mode, stopping the cpu but allowing the adc, the external interrupts, and the watchdog to continue operating (if enabled). this sleep mode halts clk i/o , clk cpu , and clk nvm , while allowing the other clocks to run. this mode improves the noise environment for the adc, enabling higher resolution measurements. if the adc is enabled, a conversion starts automati cally when this mode is entered. this mode is available in all devices, altho ugh only attiny5/10 are equipped with an adc. 7.1.3 power-down mode when bits sm2:0 are written to 010, the sleep instruct ion makes the mcu enter power-down mode. in this mode, the oscillator is stopped, while the external interrupts, and the watchdog continue operating (if enabled). only a watchdog reset, an external level interrupt on int0, or a pin change interrupt can wake up the mcu. this sleep mode halts all generated clocks, allowing operation of asynchronous modules only. 7.1.4 standby mode when bits sm2:0 are written to 100, the sleep instruction makes the mcu enter standby mode. this mode is identical to power-down with the exception that the oscilla tor is kept runnin g. this reduces wake-up time, because the oscillator is already running an d doesn't need to be started up. 7.2 power reduction register the power reduction r egister (prr), see ?prr ? power reduction register? on page 26 , provides a method to reduce power consumption by stopping the clock to i ndividual peripherals. when t he clock for a peripheral is stopped then: ? the current state of the peripheral is frozen. ? the associated registers can not be read or written. ? resources used by the peri pheral will remain occupied. the peripheral should in most cases be disabled before stopping the clock. clearing the prr bit wakes up the peripheral and puts it in the same state as before shutdown. peripheral shutdown can be used in idle mode and active mode to significantly reduce the overall power consump- tion. see ?supply current of i/o modules? on page 121 for examples. in all other sleep modes, the clock is already stopped. 7.3 minimizing power consumption there are several issues to consider when trying to mi nimize the power consumption in an avr core controlled system. in general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device?s functions are operat ing. all functions not needed should be disabled. in par- ticular, the following modules may need special consider ation when trying to achieve the lowest possible power consumption. 7.3.1 analog comparator when entering idle mode, the analog comparator should be disabled if not used. in the power-down mode, the analog comparator is automatically disabled. see ?analog comparator? on page 80 for further details. 25 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 7.3.2 analog to digital converter if enabled, the adc will be enab led in all sleep modes. to save power, the adc should be di sabled before entering any sleep mode. when the adc is turned off and on again, the next conversi on will be an extended conversion. see ?analog to digital converter? on page 82 for details on adc operation. the adc is available in attiny5/10, only. 7.3.3 watchdog timer if the watchdog timer is not needed in the application, this module should be turned off. if the watchdog timer is enabled, it will be enabled in all sleep modes, and hence, always cons ume power. in the dee per sleep modes, this will contribute significantly to the total current consumption. refer to ?watchdog timer? on page 30 for details on how to configure the watchdog timer. 7.3.4 port pins when entering a sleep mode, all port pins should be conf igured to use minimum power. the most important thing is then to ensure that no pins drive resist ive loads. in sleep modes where the i/o clock (clk i/o ) is stopped, the input buffers of the device will be disabled. th is ensures that no powe r is consumed by the in put logic when not needed. in some cases, the input logic is nee ded for detecting wa ke-up conditions, and it will th en be enabled. refer to the section ?digital input enable and sleep modes? on page 44 for details on which pins are enabled. if the input buffer is enabled and the input signal is left floati ng or has an analog signal level close to v cc /2, the input buffer will use excessive power. for analog input pins, the digital input buffer should be di sabled at all times. an analog signal level close to v cc /2 on an input pin can cause significant current even in active mode. digital input buffers ca n be disabled by writing to the digital input disable register (didr0). refer to ?didr0 ? digital input disable register 0? on page 81 for details. 7.4 register description 7.4.1 smcr ? sleep mode control register the smcr control register contains control bits for power management. ? bits 7:4 ? res: reserved bits these bits are reserved and will always read zero. ? bits 3:1 ? sm2..sm0: sleep mode select bits 2..0 these bits select between available sleep modes, as shown in table 7-2 . bit 76543210 0x3a ? ? ? ? sm2 sm1 sm0 se smcr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 7-2. sleep mode select sm2 sm1 sm0 sleep mode 000idle 0 0 1 adc noise reduction (1) 0 1 0 power-down 011reserved 1 0 0 standby 26 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 note: 1. this mode is available in all devices, although only attiny5/10 are equipped with an adc ? bit 0 ? se: sleep enable the se bit must be written to logic one to make the mcu ente r the sleep mode when the sleep instruction is exe- cuted. to avoid the mcu entering the sleep mode unless it is the programmer?s purpose, it is recommended to write the sleep enable ( se) bit to one just before the execution of the sleep instructio n and to clear it immediately after waking up. 7.4.2 prr ? power reduction register ? bits 7:2 ? res: reserved bits these bits are reserved and will always read zero. ? bit 1 ? pradc: power reduction adc writing a logic one to this bit shuts down the adc. th e adc must be disabled befor e shut down. the analog com- parator cannot use the adc input mux when the adc is shut down. the adc is available in attiny5/10, only. ? bit 0 ? prtim0: power reduction timer/counter0 writing a logic one to this bit shuts down the timer/counter0 module. when the timer/counter0 is enabled, opera- tion will continue like before the shutdown. 101reserved 110reserved 111reserved table 7-2. sleep mode select sm2 sm1 sm0 sleep mode bit 7 6 5 4 3 2 1 0 0x35 ? ? ? ? ? ? pradc prtim0 prr read/write r r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 27 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 8. system control and reset 8.1 resetting the avr during reset, all i/o registers are set to their initial values, and the program starts execution from the reset vector. the instruction placed at the reset ve ctor must be a rjmp ? relative jump ? instruction to the reset handling rou- tine. if the program never enables an interrupt source, th e interrupt vectors are not used, and regular program code can be placed at these locations. the circuit diagram in figure 8-1 shows the reset logic. electrical parameters of the reset circuitry are defined in section ?system and reset characteristics? on page 118 . figure 8-1. reset logic the i/o ports of the avr are immediately reset to their initial state when a rese t source goes active. this does not require any clock source to be running. after all reset sources have gone inactive, a delay counter is invoked, stretching the inte rnal reset. this allows the power to reach a stable level before normal operation starts. the start up sequence is described in ?starting from reset? on page 20 . 8.2 reset sources the attiny4/5/9/10 have three sources of reset: ? power-on reset. the mcu is reset when the supply voltage is below the power-on reset threshold (v pot ) ? external reset. the mcu is reset when a low level is pr esent on the reset pin for longer than the minimum pulse length ? watchdog reset. the mcu is reset when the watchdog timer period expires and the watchdog is enabled 8.2.1 power-on reset a power-on reset (por) pulse is generated by an on-chip detection circuit. the detection level is defined in sec- tion ?system and reset characteristics? on page 118 . the por is activated whenever v cc is below the detection level. the por circuit can be used to trigger the start-up reset, as well as to detect a failure in supply voltage. reset flag register (rstflr) delay counters ck timeout wdrf extrf porf data b u s clock generator spike filter pull-up resistor watchdog oscillator power-on reset circuit vlm 28 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 a power-on reset (por) circuit ensures that the device is reset from power-on. reaching the power-on reset threshold voltage invokes the delay counter, which de termines how long the device is kept in reset after v cc rise. the reset signal is activated again, without any delay, when v cc decreases below the detection level. figure 8-2. mcu start-up, reset tied to v cc figure 8-3. mcu start-up, reset extended externally 8.2.2 v cc level monitoring attiny4/5/9/10 have a v cc level monitoring (vlm) ci rcuit that compares the voltage level at the v cc pin against fixed trigger levels. the trigger le vels are set with vlm2:0 bits, see ?vlmcsr ? vcc level monitoring control and status register? on page 33 . the vlm circuit provides a status flag, vlmf, that indicates if voltage on the v cc pin is below the selected trigger level. the flag can be read from vlmcsr, but it is also possible to have an interrupt generated when the vlmf status flag is set. this interrupt is enabled by the vl mie bit in the vlmcsr regist er. the flag can be cleared by changing the trigger level or by writing it to zero. the flag is automatically cleared when the voltage at v cc rises back above the selected trigger level. the vlm can also be used to improve reset characteristic s at falling supply. without vlm, the power-on reset (por) does not activate before supply voltage has droppe d to a level where the mcu is not necessarily functional any more. with vlm, it is possible to generate a reset earlier. when active, the vlm circuit consum es some power, as illustrated in figure 17-48 on page 145 . to save power the vlm circuit can be turned off completely, or it can be switched on and off at regula r intervals. however, detec- tion takes some time and it is therefore recommended to leave the circuitry on long enough for signals to settle. see ?vcc level monitor? on page 118 . v time-out reset reset tout internal t v pot v rst cc v time-out tout tout internal cc t v pot v rst > t reset reset 29 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 when vlm is active and voltage at v cc is above the selected trigger level operation will be as normal and the vlm can be shut down for a short period of time. if voltage at v cc drops below the selected threshold the vlm will either flag an interrupt or generate a reset, depending on the configuration. when the vlm has been configured to ge nerate a reset at low supply voltage it will keep the device in reset as long as v cc is below the reset level. see table 8-4 on page 34 for reset level details. if su pply voltage rises above the reset level the condition is removed and the mcu will come out of reset, and initiate the power-up start-up sequence. if supply voltage drops enough to trigger the por then porf is set after supply voltage has been restored. 8.2.3 external reset an external reset is generat ed by a low level on the reset pin if enabled. reset pulses longer than the minimum pulse width (see section ?system and reset characteristics? on page 118 ) will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to gener ate a reset. when the applied signal reaches the reset threshold voltage ? v rst ? on its positive edge, the delay counter st arts the mcu after the time-out period ? t tout ? has expired. external reset is ignored during power-on st art-up count. after power-on reset the internal reset is extended only if reset pin is low when the initial power-on delay coun t is complete. see figure 8-2 and figure 8- 3 on page 28 . figure 8-4. external reset during operation 8.2.4 watchdog reset when the watchdog times out, it will gen erate a short reset pulse of one ck cycle duration. on the falling edge of this pulse, the delay timer starts counting the time-out period t tout . see page 30 for details on operation of the watchdog timer and table 16-4 on page 118 for details on reset time-out. cc 30 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 8-5. watchdog reset during operation 8.3 watchdog timer the watchdog timer is clocked from an on-chip oscillator, which runs at 128 khz. see figure 8-6 . by controlling the watchdog timer prescaler, the watchdog reset interval can be adjusted as shown in table 8-2 on page 32 . the wdr ? watchdog reset ? instruction resets the watchdog timer. the watchdog timer is also reset when it is disabled and when a device reset occurs. ten different cl ock cycle periods can be selected to determine the reset period. if the reset period expires without another watchdog reset, the attiny4/5/9/10 resets and executes from the reset vector. for timing details on the watchdog reset, refer to table 8-3 on page 33 . figure 8-6. watchdog timer the wathdog timer can also be configured to generate an interrupt instead of a reset. this can be very helpful when using the watchdog to wake-up from power-down. to prevent unintentional disabling of the watchdog or unin tentional change of time-out period, two different safety levels are selected by the fuse wdton as shown in table 8-1 on page 31 . see ?procedure for changing the watchdog timer configuration? on page 31 for details. ck cc osc/2k osc/4k osc/8k osc/16k osc/32k osc/64k osc/128k osc/256k osc/512k osc/1024k mcu reset watchdog prescaler 128 khz oscillator watchdog reset wdp0 wdp1 wdp2 wdp3 wde mux 31 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 8.3.1 procedure for changing the watchdog timer configuration the sequence for changing configuration differs between the two safety levels, as follows: 8.3.1.1 safety level 1 in this mode, the watchdog timer is in itially disabled, but can be enabled by writing the wde bit to one without any restriction. a special sequence is needed when disabli ng an enabled watchdog timer. to disable an enabled watchdog timer, the following procedure must be followed: 1. write the signature for change enable of protected i/o registers to register ccp 2. within four instruction cycles, in the same operation, write wde and wdp bits 8.3.1.2 safety level 2 in this mode, the watchdog timer is always enabled, and the wde bit will a lways read as one. a protected change is needed when changing the watchdog time-out period . to change the watchdog time -out, the following proce- dure must be followed: 1. write the signature for change enable of protected i/o registers to register ccp 2. within four instruction cycle s, write the wdp bit. the value written to wde is irrelevant 8.3.2 code examples the following code example shows how to turn off the wd t. the example assumes that interrupts are controlled (e.g., by disabling interrup ts globally) so that no in terrupts will occur during ex ecution of these functions. note: see ?code examples? on page 5 . table 8-1. wdt configuration as a function of the fuse settings of wdton wdton safety level wdt initial state how to disable the wdt how to change time-out unprogrammed 1 disabled protected change sequence no limitations programmed 2 enabled always enabled protected change sequence assembly code example wdt_off: wdr ; clear wdrf in rstflr in r16, rstflr andi r16, ~(1< 33 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 ? bits 5, 2:0 ? wdp3..0: watchdog timer prescaler 3, 2, 1 and 0 the wdp3..0 bits determine the watchdog timer prescaling when the watchdog timer is running. the different prescaling values and their corresponding time-out periods are shown in table 8-3 on page 33 . 8.4.2 vlmcsr ? v cc level monitoring control and status register ? bit 7 ? vlmf: vlm flag this bit is set by the vlm circuit to indicate t hat a voltage level condition has been triggered (see table 8-4 ). the bit is cleared when the trigger level selection is set to ?disabled?, or when voltage at v cc rises above the selected trigger level. ? bit 6 ? vlmie: vlm interrupt enable when this bit is set the vlm interrupt is enabled. a vlm interrupt is generated every time the vlmf flag is set. ? bits 5:3 ? res: reserved bits these bits are reserved. for en suring compatibility with fu ture devices, these bits must be written to zero, when the register is written. ? bits 2:0 ? vlm2:0: trigger level of voltage level monitor these bits set the trigger level for the voltage level monitor, as described in table 8-4 below. table 8-3. watchdog timer prescale select wdp3 wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at v cc = 5.0v 0 0 0 0 2k (2048) cycles 16 ms 0 0 0 1 4k (4096) cycles 32 ms 0 0 1 0 8k (8192) cycles 64 ms 0 0 1 1 16k (16384 ) cycles 0.125 s 0 1 0 0 32k (32768) cycles 0.25 s 0 1 0 1 64k (65536) cycles 0.5 s 0 1 1 0 128k (131072) cycles 1.0 s 0 1 1 1 256k (262144) cycles 2.0 s 1 0 0 0 512k (524288) cycles 4.0 s 1 0 0 1 1024k (1048576) cycles 8.0 s 1010 reserved 1011 1100 1101 1110 1111 bit 76543210 0x34 vlmf vlmie ? ? ? vlm2 vlm1 vlm0 vlmcsr read/write r r/w r r r r/w r/w r/w initial value00000000 34 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 for vlm voltage levels, see table 16-6 on page 118 . 8.4.3 rstflr ? reset flag register the reset flag register provides information on which reset source caused an mcu reset. ? bits 7:4, 2? res: reserved bits these bits are reserved bits in attiny 4/5/9/10 and will always read as zero. ? bit 3 ? wdrf: watchdog reset flag this bit is set if a watchdog reset occurs. the bit is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 1 ? extrf: external reset flag this bit is set if an external reset occurs. the bit is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 0 ? porf: power-on reset flag this bit is set if a power-on reset occurs. the bit is reset only by writing a logic zero to the flag. to make use of the reset flags to identify a reset condition, the user should read and then reset the mcusr as early as possible in the program. if the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. table 8-4. setting the trigger level of voltage level monitor. vlm2:0 label description 000 vlm0 voltage level monitor disabled 001 vlm1l triggering generates a regu lar power-on reset (por). the vlm flag is not set 010 vlm1h 011 vlm2 triggering sets the vlm flag (vlmf) and generates a vlm interrupt, if enabled 100 vlm3 101 not allowed 110 111 bit 76543210 0x3b ? ? ? ?wdrf ? extrf porf rstflr read/write r r r r r/w r r/w r/w initial value 0 0 0 0 x 0 x x 35 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 9. interrupts this section describes the specifics of the interrupt han dling in attiny4/5/9/10. for a general explanation of the avr interrupt handling, see ?reset and interrupt handling? on page 10 . 9.1 interrupt vectors interrupt vectors of attiny4/5/9/10 are described in table 9-1 below. note: 1. the adc is available in attiny5/10, only. in case the program never enables an interrupt source, the interrupt vectors will not be used and, consequently, regular program code can be placed at these locations. the most typical and general setup for interrupt vector ad dresses in attiny4/5/9/10 is shown in the program exam- ple below. address labels code comments 0x0000 rjmp reset ; reset handler 0x0001 rjmp int0 ; irq0 handler 0x0002 rjmp pcint0 ; pcint0 handler 0x0003 rjmp tim0_capt ; timer0 capture handler 0x0004 rjmp tim0_ovf ; timer0 overflow handler 0x0005 rjmp tim0_compa ; timer0 compare a handler 0x0006 rjmp tim0_compb ; timer0 compare b handler 0x0007 rjmp ana_comp ; analog comparator handler 0x0008 rjmp wdt ; watchdog interrupt handler 0x0009 rjmp vlm ; voltage level monitor handler 0x000a rjmp adc ; adc conversion handler 36 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 0x000b reset: ldi r16, high(ramend); main program start 0x000c out sph,r16 ; set stack pointer 0x000d ldi r16, low(ramend) ; to top of ram 0x000e out spl,r16 0x000f sei ; enable interrupts 0x0010 37 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 9-1. timing of pin change interrupts 9.3 register description 9.3.1 eicra ? external inte rrupt control register a the external interrupt control register a cont ains control bits for interrupt sense control. ? bits 7:2 ? res: reserved bits these bits are reserved and will always read zero. ? bits 1:0 ? isc01, isc00: interrupt sense control 0 bit 1 and bit 0 the external interrupt 0 is activated by the external pi n int0 if the sreg i-flag and the corresponding interrupt mask are set. the level and edges on the external int0 pin that activate the interrupt are defined in table 9-2 . the value on the int0 pin is sampled before detecting edges. if ed ge or toggle interrupt is se lected, pulses that last lon- ger than one clock period will generate an interrupt. shorter pulses are not guaranteed to ge nerate an in terrupt. if clk pcint(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag pcif pcint(0) pin_sync pcint_syn pin_lat d q le pcint_setflag pcif clk clk pcint(0) in pcmsk(x) pcint_in_(0) 0 x bit 76543210 0x15 ? ? ? ? ? ? isc01 isc00 eicra read/write rrrrrrr/wr/w initial value00000000 38 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 low level interrupt is selected , the low level must be held until the completion of the currently executing instruction to generate an interrupt. 9.3.2 eimsk ? external interrupt mask register ? bits 7:1 ? res: reserved bits these bits are reserved and will always read zero. ? bit 0 ? int0: external interrupt request 0 enable when the int0 bit is set (one) and the i-bit in the status register (sreg) is set (one), the external pin interrupt is enabled. the interrupt sense control bits (isc01 and isc0 0) in the external interrupt control register a (eicra) define whether the external interrupt is activated on rising and/or fa lling edge of the int0 pin or level sensed. activ- ity on the pin will cause an interrupt req uest even if int0 is configured as an output. the corres ponding interrupt of external interrupt request 0 is execut ed from the int0 interrupt vector. 9.3.3 eifr ? external interrupt flag register ? bits 7:1 ? res: reserved bits these bits are reserved and will always read zero. ? bit 0 ? intf0: external interrupt flag 0 when an edge or logic change on the int0 pin triggers an interrupt request, intf0 becomes set (one). if the i-bit in sreg and the int0 bi t in eimsk are set (one), the mcu will jump to the corr esponding inte rrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. this flag is constantly zero when in t0 is configured as a level interrupt. table 9-2. interrupt 0 sense control isc01 isc00 description 0 0 the low level of int0 generates an interrupt request. 0 1 any logical change on int0 generates an interrupt request. 1 0 the falling edge of int0 gen erates an interrupt request. 1 1 the rising edge of int0 generates an interrupt request. bit 76543210 0x13 ? ? ? ? ? ? ?intoeimsk read/write rrrrrrrr/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x14 ? ? ? ? ? ? ?intf0eifr read/write rrrrrrrr/w initial value 0 0 0 0 0 0 0 0 39 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 9.3.4 pcicr ? pin change in terrupt control register ? bits 7:1 ? res: reserved bits these bits are reserved and will always read zero. ? bit 0 ? pcie0: pin change interrupt enable 0 when the pcie0 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt 0 is enabled. any change on any enabled pcint3..0 pin will caus e an interrupt. th e corresponding in terrupt of pin change interrupt request is executed fr om the pci0 interrupt vector. pcin t3..0 pins are enabled individually by the pcmsk register. 9.3.5 pcifr ? pin change interrupt flag register ? bits 7:1 ? res: reserved bits these bits are reserved and will always read zero. ? bit 0 ? pcif0: pin change interrupt flag 0 when a logic change on any pcint3..0 pin triggers an interrupt request, pcif0 becomes set (one). if the i-bit in sreg and the pcie0 bit in pcicr are se t (one), the mcu will jump to the co rresponding interrup t vector. the flag is cleared when the interrupt routine is ex ecuted. alternatively, the flag can be cleared by writing a logical one to it. 9.3.6 pcmsk ? pin change mask register ? bits 7:4 ? res: reserved bits these bits are reserved and will always read zero. ? bits 3:0 ? pcint3..0: pin change enable mask 3..0 each pcint3..0 bit selects whether pin change interr upt is enabled on the corresponding i/o pin. if pcint3..0 is set and the pcie0 bit in pcicr is set, pin change interrupt is enabled on the corresponding i/o pin. if pcint3..0 is cleared, pin change interrupt on the corresponding i/o pin is disabled. bit 76543210 0x12 ? ? ? ? ? ? ? pcie0 pcicr read/write rrrrrrrr/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x11 ? ? ? ? ? ? ? pcif0 pcifr read/write rrrrrrrr/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x10 ? ? ? ? pcint3 pcint2 pcint1 pcint0 pcmsk read/write r r r r r/w r/w r/w r/w initial value00000000 40 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 10. i/o ports 10.1 overview all avr ports have true read-modify-write functionality wh en used as general digital i/o ports. this means that the direction of one port pin can be changed without unin tentionally changing the direction of any other pin with the sbi and cbi instructions. the same applies when changing drive value (if configured as output) or enabling/dis- abling of pull-up resistors. each output buffer has symmetr ical drive characteristics with both high sink and source capability. the pin driver is strong enough to drive led disp lays directly. all port pins have individually selectable pull-up resistors with a supply-volt age invariant resistance. all i/o pins have prot ection diodes to both v cc and ground as indicated in figure 10-1 on page 40 . see ?electrical characteristics? on page 115 for a complete list of parameters. figure 10-1. i/o pin equivalent schematic all registers and bit references in this section are writt en in general form. a lower case ?x? represents the number- ing letter for the port, and a lower case ?n? represents t he bit number. however, when using the register or bit defines in a program, the precise form must be used. for example, portb3 for bit no. 3 in port b, here docu- mented generally as portxn. the physical i/o registers and bit locations are listed in ?register description? on page 50 . four i/o memory address locations are allocated for each port, one each for the data register ? portx, data direction register ? ddrx, pull-up enable register ? pu ex, and the port input pins ? pinx. the port input pins i/o location is read only, while the data register, the data direction register, and the pull-up enable register are read/write. however, writing a logic one to a bit in the pinx register, will re sult in a toggle in the correspo nding bit in the data register. using the i/o port as general digital i/o is described in ?ports as general digital i/o? on page 41 . most port pins are multiplexed with alternate functions for the peripheral features on the device. how each alternate function inter- feres with the port pin is described in ?alternate port functions? on page 45 . refer to the individual module sections for a full description of the alternate functions. note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital i/o. c pin logic r p u s ee fig u re "gener a l digit a l i/o" for det a il s pxn 41 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 10.2 ports as general digital i/o the ports are bi-directional i/o ports with optional internal pull-ups. figure 10-2 shows a functional description of one i/o-port pin, here generically called pxn. figure 10-2. general digital i/o (1) note: 1. wex, wrx, wpx, wdx, rex, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , and sleep are common to all ports. 10.2.1 configuring the pin each port pin consists of four register bits: ddxn, portxn, puexn, an d pinxn. as shown in ?register description? on page 50 , the ddxn bits are accessed at the ddrx i/o addre ss, the portxn bits at th e portx i/o address, the puexn bits at the puex i/o address, and the pinxn bits at the pinx i/o address. the ddxn bit in the ddrx register select s the direction of this pin. if ddxn is written logic one, pxn is configured as an output pin. if ddxn is written logic zero, pxn is configured as an input pin. clk rpx rrx rdx wdx wex synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin clk i/o : i/o clock rdx: read ddrx wex: write puex rex: read puex d l q q rex reset reset q q d q qd clr portxn q qd clr ddxn pinxn data bus sleep sleep: sleep control pxn i/o wpx reset q qd clr puexn 0 1 wrx wpx: write pinx register 42 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 if portxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). if portxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). the pull-up resistor is activated, if th e puexn is written logic one. to switch the pull-up resistor off, puexn has to be written logic zero. table 10-1 summarizes the control signals for the pin value. port pins are tri-stated when a reset condition be comes active, even when no clocks are running. 10.2.2 toggling the pin writing a logic one to pinxn toggles the value of portxn , independent on the value of ddrxn. note that the sbi instruction can be used to toggle one single bit in a port. 10.2.3 break-before-make switching in break-before-make mode, switching the ddrxn bit from input to output introduces an immediate tri-state period lasting one system clock cy cle, as indicated in figure 10-3 . for example, if the system clock is 4 mhz and the ddrxn is written to make an output, an immediate tri-st ate period of 250 ns is introduced before the value of portxn is seen on the port pin. to avoid glitches it is recommended that the maximu m ddrxn toggle frequency is two system clock cycles. the break-before-make mode applies to the entire port and it is activated by the bbmx bit. for more details, see ?portcr ? port control register? on page 50 . when switching the ddrxn bit from output to input no immedi ate tri-state period is introduced. table 10-1. port pin configurations ddxn portxn puexn i/o pull-up comment 0x 0 input no tri-state (hi-z) 0x 1 input yes sources current if pulled low externally 10 0 output no output low (sink) 10 1 output yes not recommended. output low (sink) and internal pull-up active. sources current through the internal pull-up resistor and consumes power constantly 11 0 output no output high (source) 11 1 output yes output high (source) and internal pull-up active 43 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 10-3. switching between input and output in break-before-make-mode 10.2.4 reading the pin value independent of the setting of data direction bit ddxn, t he port pin can be read through the pinxn register bit. as shown in figure 10-2 on page 41 , the pinxn register bit and the preceding latch constitute a synchronizer. this is needed to avoid metastability if the physica l pin changes value near the edge of th e internal clock, but it also intro- duces a delay. figure 10-4 shows a timing diagram of the synchronizat ion when reading an externally applied pin value. the maximum and minimum propagation delays are denoted t pd,max and t pd,min respectively. figure 10-4. synchronization when reading an externally applied pin value consider the clock period starting shortly after the first falling edge of the system clock. the latch is closed when the clock is low, and goes transpar ent when the clock is high, as indicated by the sh aded region of the ?sync latch? signal. the signal value is latche d when the system clock goes low. it is clocked into the pinxn register at the succeeding positive clock edge. as indicated by the tw o arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ? and 1? system cl ock period depend ing upon the time of assertion. when reading back a software assigned pin value, a nop instruction must be inserted as indicated in figure 10-5 on page 44 . the out instruction sets the ?sync latch? signal at the positive edge of the clock. in this case, the delay tpd through the synchroniz er is one system clock period. out ddrx, r16 nop 0x02 0x01 system clk instructions ddrx intermediate tri-state cycle out ddrx, r17 0x55 portx 0x01 intermediate tri-state cycle px0 px1 tri-state tri-state tri-state 0x01 r17 0x02 r16 xxx in r17, pinx 0x00 0xff instructions sync latch pinxn r17 xxx system clk t pd, max t pd, min 44 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 10-5. synchronization when reading a software assigned pin value 10.2.5 digital input enable and sleep modes as shown in figure 10-2 on page 41 , the digital input signal can be clamped to ground at the input of the schmitt- trigger. the signal denoted sleep in the figure, is set by the mcu sleep controller in power-down and standby modes to avoid high power consumption if some input signals are left floating, or have an analog signal level close to v cc /2. sleep is overridden for port pins enabled as external inte rrupt pins. if the external in terrupt request is not enabled, sleep is active also for these pins. sl eep is also overridden by various other alternate function s as described in ?alternate port functions? on page 45 . if a logic high level (?one?) is present on an asynchronous external interrupt pin configured as ?interrupt on rising edge, falling edge, or any logic change on pin? while the external interrupt is not enabled, the corresponding external interrupt flag will be set when resuming from the above mentioned sl eep mode, as the cl amping in these sleep mode produces the requested logic change. 10.2.6 unconnected pins if some pins are unused, it is recommended to ensure that these pins have a defined level. even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where t he digital inputs are enabled (reset, active mode and idle mode). the simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. in this case, the pull-up will be disabled during reset. if low power consumpt ion during reset is importan t, it is recommended to use an external pull-up or pulldown. c onnecting unused pins directly to v cc or gnd is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output. out portx, r16 nop in r17, pinx 0xff 0x00 0xff system clk r16 instructions sync latch pinxn r17 t pd 45 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 10.2.7 program example the following code example shows how to set port b pin 0 high, pin 1 low, and define the port pins from 2 to 3 as input with a pull-up assigned to port pin 2. the resulting pi n values are read back agai n, but as previously dis- cussed, a nop instruction is included to be able to read back t he value recently assigned to some of the pins. note: see ?code examples? on page 5 . 10.3 alternate port functions most port pins have alternate functions in addition to being general digital i/os. in figure 10-6 below is shown how the port pin control signals from the simplified figure 10-2 on page 41 can be overridden by alternate functions. assembly code example ... ; define pull-ups and set outputs high ; define directions for port pins ldi r16,(1< 47 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 table 10-2 on page 47 summarizes the function of the overriding signals. the pin and port indexes from figure 10- 6 on page 46 are not shown in the succeeding tables. the overriding signals are generated internally in the mod- ules having the alternate function. the following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. refer to the alternat e function description for further details. table 10-2. generic description of overriding signals for alternate functions signal name full name description puoe pull-up override enable if this signal is set, the pull-up enable is controlled by the puov signal. if this signal is cleared, the pull-up is enabled when puexn = 0b1. puov pull-up override value if puoe is set, the pull-up is enabled/disabled when puov is set/cleared, regardless of the setting of the puexn register bit. ddoe data direction override enable if this signal is set, the output driver enable is controlled by the ddov signal. if this signal is cl eared, the output driver is enabled by the ddxn register bit. ddov data direction override value if ddoe is set, the output dr iver is enabled/disabled when ddov is set/cleared, regardless of the setting of the ddxn register bit. pvoe port value override enable if this signal is set and the output driver is enabled, the port value is controlled by the pvov signal. if pvoe is cleared, and the output driver is enabled, the port value is controlled by the portxn register bit. pvov port value override value if pvoe is set, the port value is set to pvov, regardless of the setting of the portxn register bit. ptoe port toggle override enable if ptoe is set, the portxn register bit is inverted. dieoe digital input enable override enable if this bit is set, the digital input enable is controlled by the dieov signal. if this signal is cleared, the digital input enable is determined by mcu state (normal mode, sleep mode). dieov digital input enable override value if dieoe is set, the digital input is enabled/disabled when dieov is set/cleared, regard less of the mcu state (normal mode, sleep mode). di digital input this is the digital input to alte rnate functions. in the figure, the signal is connected to the output of the schmitt-trigger but before the synchronizer. unless the digital input is used as a clock source, the module with the alternate function will use its own synchronizer. aio analog input/output this is the analog input/output to /from alternate functions. the signal is connected directly to the pad, and can be used bi- directionally. 48 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 10.3.1 alternate functions of port b the port b pins with alternate function are shown in table 10-3 on page 48 . ? port b, bit 0 ? adc0/ain0/oc0a/pcint0/tpidata ? adc0: analog to digital converter, channel 0 (attiny5/10, only) ? ain0: analog comparator positive input. configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interferin g with the function of the analog comparator. ? oc0a, output compare match output: the pb0 pin can serve as an external output for the timer/counter0 compare match a. the pin has to be configured as an out put (ddb0 set (one)) to serve this function. this is also the output pin for the pwm mode timer function. ? pcint0: pin change interrupt source 0. the pb0 pin ca n serve as an external interrupt source for pin change interrupt 0. ? tpidata: serial programming data. ? port b, bit 1 ? adc1/ain1/cl ki/icp0/oc0b/pc int1/tpiclk ? adc1: analog to digital converter, channel 1 (attiny5/10, only) ? ain1: analog comparator negative inpu t. configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interferin g with the function of the analog comparator. ? clki: external clock. ? icp0: input capture pin. the pb1 pin can act as an input capture pin for timer/counter0. ? oc0b: output compare match output: the pb1 pin can serve as an external output for the timer/counter0 compare match b. the pb1 pin has to be configured as an output (ddb1 set (one)) to serve this function. the oc0b pin is also the output pin for the pwm mode timer function. table 10-3. port b pins alternate functions port pin alternate function pb0 adc0: adc input channel 0 ain0: analog comparator, positive input oc0a: timer/counter0 compare match a output pcint0: pin change interrupt 0, source 0 tpidata:serial programming data pb1 adc1: adc input channel 1 ain1: analog comparator, negative input clki: external clock icp0: timer/counter0 input capture input oc0b: timer/counter0 compare match b output pcint1:pin change interrupt 0, source 1 tpiclk: serial programming clock pb2 adc2: adc input channel 2 clko: system clock output int0: external interrupt 0 source pcint2: pin change interrupt 0, source 2 t0: timer/counter0 clock source pb3 adc3: adc input channel 3 pcint3: pin change interrupt 0, source 3 reset :reset pin 49 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 ? pcint1: pin change interrupt source 1. the pb1 pin ca n serve as an external interrupt source for pin change interrupt 0. ? tpiclk: serial programming clock. ? port b, bit 2 ? adc2/clko/int0/pcint2/t0 ? adc2: analog to digital converter, channel 2 (attiny5/10, only) ? clko: system clock output. the system clock can be ou tput on pin pb2. the system clock will be output if ckout bit is programmed, regardless of the portb2 and ddb2 settings. ? int0: external interrupt request 0 ? pcint2: pin change interrupt source 2. the pb2 pin ca n serve as an external interrupt source for pin change interrupt 0. ? t0: timer/counter0 counter source. ? port b, bit 3 ? adc3/pcint3/reset ? adc3: analog to digital converter, channel 3 (attiny5/10, only) ? pcint3: pin change interrupt source 3. the pb3 pin ca n serve as an external interrupt source for pin change interrupt 0. ? reset : table 10-4 and table 10-5 on page 50 relate the alternate functions of port b to the overriding signals shown in figure 10-6 on page 46 . table 10-4. overriding signals for alternate functions in pb3..pb2 notes: 1. rstdisbl is 1 when the configuration bit is ?0? (programmed). 2. ckout is 1 when the configuration bit is ?0? (programmed). signal name pb3/adc3/reset /pcint3 pb2/adc2/int0/t0/clko/pcint2 puoe rstdisbl (1) ckout (2) puov 1 0 ddoe rstdisbl (1) ckout (2) ddov 0 1 pvoe 0 ckout (2) pvov 0 (system clock) ptoe 0 0 dieoe rstdisbl (1) + (pcint3 ? pcie0) + adc3d (pcint2 ? pcie0) + adc2d + int0 dieov rstdisbl ? pcint3 ? pc ie0 (pcint2 ? pcie0) + int0 di pcint3 input int0/t0/pcint2 input aio adc3 input adc2 input 50 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 notes: 1. ext_clock is 1 when external clock is selected as main clock. 10.4 register description 10.4.1 portcr ? port control register ? bits 7:2, 0 ? reserved these bits are reserved and will always read zero. ? bit 1 ? bbmb: break-before-make mode enable when this bit is set the brea k-before-make mode is activated for the enti re port b. the intermediate tri-state cycle is then inserted when writing ddrxn to make an output. for further information, see ?break-before-make switch- ing? on page 42 . 10.4.2 pueb ? port b pull- up enable control register table 10-5. overriding signals for alternate functions in pb1..pb0 signal name pb1/adc1/ain1/oc0b/clki/icp0/p cint1 pb0/adc0/ain0/oc0a/pcint0 puoe ext_clock (1) 0 puov 0 0 ddoe ext_clock (1) 0 ddov 0 0 pvoe ext_clock (1) + oc0b enable oc0a enable pvov ext_clock (1) ? oc0b oc0a ptoe 0 0 dieoe ext_clock (1) + (pcint1 ? pcie0) + adc1d (pcint0 ? pcie0) + adc0d dieov (ext_clock (1) ? pwr_down ) + (ext_clock (1) ? pcint1 ? pcie0) pcint0 ? pcie0 di clock/icp0/pcint1 input pcint0 input aio adc1/analog comparator negative input a dc0/analog comparator positive input bit 7 6 5 4 3 2 1 0 0x03 ? ? ? ? ? ? bbmb ?portcr read/write r r r r r r r/w r initial value 0 0 0 0 0 0 0 0 bit 76543210 0x03 ? ? ? ? pueb3 pueb2 pueb1 pueb0 pueb read/write r r r r r/w r/w r/w r/w initial value00000000 51 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 10.4.3 portb ? port b data register 10.4.4 ddrb ? port b da ta direction register 10.4.5 pinb ? po rt b input pins bit 76543210 0x02 ? ? ? ? portb3 portb2 portb1 portb0 portb read/write r r r r r/w r/w r/w r/w initial value00000000 bit 76543210 0x01 ? ? ? ? ddb3 ddb2 ddb1 ddb0 ddrb read/write r r r r r/w r/w r/w r/w initial value00000000 bit 76543210 0x00 ? ? ? ? pinb3 pinb2 pinb1 pinb0 pinb read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 n/a n/a n/a n/a 52 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 11. 16-bit timer/counter0 11.1 features ? true 16-bit design, including 16-bit pwm ? two independent output compare units ? double buffered output compare registers ? one input capture unit ? input capture noise canceler ? clear timer on compare match (auto reload) ? glitch-free, phase correct pulse width modulator (pwm) ? variable pwm period ? frequency generator ? external event counter ? four independent interrupt sources (tov0, ocf0a, ocf0b, and icf0) 11.2 overview the 16-bit timer/counter unit allows accurate program execution timing (event man agement), wave generation, and signal timing measurement. figure 11-1. 16-bit timer/counter block diagram clock s elect timer/co u nter data b u s ocrna ocrnb icrn = = tcntn w a veform gener a tion w a veform gener a tion ocna ocnb noi s e c a nceler icpn = fixed top v a l u e s edge detector control logic = 0 top bottom co u nt cle a r direction tovn (int.req.) ocna (int.req.) ocnb (int.req.) icfn (int.req.) tccrna tccrnb ( from an a log comp a r a tor o u p u t ) tn edge detector ( from pre s c a ler ) clk tn 53 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 a simplified block diagram of the 16-bit timer/counter is shown in figure 11-1 on page 52 . for actual placement of i/o pins, refer to ?pinout of attiny4/5/9/10? on page 2 . cpu accessible i/o register s, including i/o bits and i/o pins, are shown in bold. the device-specific i/o register and bit locations are listed in the ?register description? on page 72 . most register and bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number, and a lower case ?x? replaces the ou tput compare unit channel. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt0 for accessing timer/counter0 counter value and so on. 11.2.1 registers the timer/counter (tcnt0), output compare registers (ocr0a/b), and input capture register (icr0) are all 16-bit registers. special procedures must be followed w hen accessing the 16-bit registers. these procedures are described in the section ?accessing 16-bit registers? on page 70 . the timer/counter control registers (tccr0a/b) are 8-bit registers and have no cpu access rest rictions. interrupt requests (abbreviat ed to int.req. in the figure) signals are all visible in the timer interrupt flag register (tifr). all inte rrupts are individually masked with the timer interrupt mask register (timsk). tifr and timsk are not shown in the figure. the timer/counter can be clocked internally, via the prescale r, or by an external cloc k source on the t0 pin. the clock select logic block controls which clock source and edge the timer/counter uses to increment (or decrement) its value. the timer/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clkt 0 ). the double buffered output compare registers (ocr0a/b) ar e compared with the timer/counter value at all time. the result of the compare can be used by the waveform generator to generate a pwm or variable frequency out- put on the output compare pin (oc0a/b). see ?output compare units? on page 58 . the compare match event will also set the compare match flag (ocf0a/b) which can be used to generate an output compare interrupt request. the input capture register can capt ure the timer/counter va lue at a given external (edge triggered) event on either the input capture pin (icp0) or on the analog comparator pins (see ?analog comparator? on page 80 ). the input capture unit includes a digital filtering unit (noise canceler) for reducing the chance of capturing noise spikes. the top value, or maximum timer/counter value, can in some modes of operation be defined by either the ocr0a register, the icr0 register, or by a set of fixed values. when using ocr0a as top value in a pwm mode, the ocr0a register can not be used for generating a pwm output. however, the top value will in this case be double buffered allowing the top value to be changed in run time. if a fixed to p value is required, the icr0 register can be used as an alternative, freeing the ocr0a to be used as pwm output. 11.2.2 definitions the following definitions are used extensively throughout the section: table 11-1. definitions constant description bottom the counter reaches bo ttom when it becomes 0x00 max the counter reaches its maximum wh en it becomes 0xff (decimal 255) top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr0a register. the assignment depends on the mode of operation 54 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 11.3 clock sources the timer/counter can be clocked by an internal or an ex ternal clock source. the clock source is selected by the clock select logic which is controlled by the clock select (cs02:0) bits loca ted in the timer/counter control regis- ter b (tccr0b). for details on clock sources and prescaler, see section ?prescaler?. 11.3.1 prescaler the timer/counter can be clocked direct ly by the system clock (by setting the cs2:0 = 1). this provides the fastest operation, with a maximum timer/counter clock frequency equal to system clock frequency (f clk_i/o ). alternatively, one of four taps from the prescaler can be used as a clock source. see figure 11-2 for an illustration of the prescaler unit. figure 11-2. prescaler for timer/counter0 note: 1. the synchronization logic on the input pins ( t0) is shown in figure 11-3 on page 55 . the prescaled clock has a frequency of f clk_i/o /8, f clk_i/o /64, f clk_i/o /256, or f clk_i/o /1024. see table 11-6 on page 75 for details. 11.3.1.1 prescaler reset the prescaler is free running, i.e., operates independently of the clock select logic of the timer/countercounter, and it is shared by the timer/counter tn. since the presca ler is not affected by the ti mer/counter?s clock select, the state of the prescaler will have implications for si tuations where a prescaled clock is used. one example of prescaling artifacts occurs when the timer is enabled and cl ocked by the prescaler (cs2:0 = 2, 3, 4, or 5). the num- ber of system clock cycles from when the timer is enable d to the first count occurs can be from 1 to n+1 system clock cycles, where n equals the prescaler divisor (8, 64, 256, or 1024). it is possible to use the presca ler reset for synchronizing the timer/counter to program execution. psr10 clear clk t0 t0 clk i/o synchronization 55 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 11.3.2 external clock source an external clock source applied to the t0 pin can be used as timer/counter clock (clk tn ). the tn pin is sampled once every system clock cycle by th e pin synchronization logic. the sync hronized (sampled) signal is then passed through the edge detector. figure 11-3 on page 55 shows a functional equivalent block diagram of the t0 synchro- nization and edge detector logic. the registers are clocked at the positive edge of the internal system clock ( clk i/o ). the latch is transparent in the high period of the internal system clock. the edge detector generates one clk t 0 pulse for each positive (cs2:0 = 7) or negative (cs2:0 = 6) edge it detects. figure 11-3. t0 pin sampling the synchronization and edge detector logic introduces a dela y of 2.5 to 3.5 system clock cycles from an edge has been applied to the t0 pin to the counter is updated. enabling and disabling of the clock input must be done when t0 has been stable for at least one system clock cycle, otherwise it is a risk that a fa lse timer/counter clock pulse is generated. each half period of the external clock applied must be longer than one system clock cycle to ensure correct sam- pling. the external clock must be guaranteed to have less than half the system clock frequency (f extclk < f clk_i/o /2) given a 50/50% duty cycle. since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (nyquist sampling theorem). however, due to variation of the system clock frequency and duty cycle caused by oscillator source (crystal , resonator, and capacitors) tolerances, it is rec- ommended that maximum frequency of an external clock source is less than f clk_i/o /2.5. an external clock source can not be prescaled. 11.4 counter unit the main part of the 16-bit timer/counter is t he programmable 16-bit bi-d irectional counter unit. figure 11-4 on page 55 shows a block diagram of the counter and its surroundings. figure 11-4. counter unit block diagram signal description (internal signals): tn_sync (to clock select logic) edge detector synchronization dq dq le dq tn clk i/o temp ( 8 -bit) data b u s ( 8 -bit) tcntn (16-bit co u nter) tcntnh ( 8 -bit) tcntnl ( 8 -bit) control logic co u nt cle a r direction tovn (int.req.) clock s elect top bottom tn edge detector ( from pre s c a ler ) clk tn 56 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 count increment or decrement tcnt0 by 1. direction select between increment and decrement. clear clear tcnt0 (set all bits to zero). clk t 0 timer/counter clock. top signalize that tcnt0 ha s reached maximum value. bottom signalize that tcnt0 has re ached minimum value (zero). the 16-bit counter is mapped into two 8-bit i/o memory locations: counter high (tcnt0h) containing the upper eight bits of the counter, an d counter low (tcnt0l) containing the lo wer eight bits. the tcnt0h register can only be indirectly accessed by the cpu. when the cpu does an access to the tcnt0h i/o location, the cpu accesses the high byte temporary register (temp). the temporary register is updated with the tcnt0h value when the tcnt0l is read, and tcnt0h is updated with the temporary register value when tcnt0l is written. this allows the cpu to read or write the entire 16-bit counter value within one cl ock cycle via the 8- bit data bus. it is important to notice that there are special cases of writi ng to the tcnt0 register when the counter is counting that will give unpredictable results. the special cases are descr ibed in the sections wher e they are of importance. depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk t 0 ). the clk t 0 can be generated from an external or internal clock source, selected by the clock select bits (cs02:0). when no clock source is se lected (cs02:0 = 0) the timer is stopped. however, the tcnt0 value can be accessed by the cpu, in dependent of whether clk t 0 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the waveform generati on mode bits (wgm03:0) located in the timer/counter control registers a and b (tccr0a and tccr0b). there are close connections between how the counter behaves (counts) and how waveforms are ge nerated on the output compare outputs oc0x. for more details about advanced counting seque nces and waveform generation, see ?modes of operation? on page 61 . the timer/counter overflow flag (tov0) is set according to the mode of oper ation selected by the wgm03:0 bits. tov0 can be used for generating a cpu interrupt. 11.5 input capture unit the timer/counter incorporates an input capture unit that can capture external events and give them a time- stamp indicating time of occurrence. the external signal indicating an event, or multiple events, can be applied via the icp0 pin. the time-stamps can then be used to calculate frequency, duty- cycle, and other features of the signal applied. alternatively the time-stamps can be used for creating a log of the events. the input capture unit is illustrate d by the block diagram shown in figure 11-5 on page 57 . the elements of the block diagram that are not directly a part of the input c apture unit are gray shaded. t he lower case ?n? in register and bit names indicates the timer/counter number. 57 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 11-5. input capture unit block diagram when a change of the logic level (an event) occurs on the input capture pin (icp0), alternatively on the analog comparator outp ut (aco), and this change confirms to the settin g of the edge detector, a capture will be triggered. when a capture is triggered, the 16-bit value of the count er (tcnt0) is written to the input capture register (icr0). the input capture flag (icf0) is set at the same system clock as the tcnt0 value is copied into icr0 register. if enabled (icie0 = 1), the input capture flag gene rates an input capture interrupt. the icf0 flag is auto- matically cleared when the interrupt is executed. alternatively the icf0 flag c an be cleared by software by writing a logical one to its i/o bit location. reading the 16-bit value in the input capture register (icr0) is done by first reading the low byte (icr0l) and then the high byte (icr0h). when the low byte is read t he high byte is copied into the high byte temporary register (temp). when the cpu reads th e icr0h i/o location it will access the temp register. the icr0 register can only be written when using a waveform generation mode that utilizes the icr0 register for defining the counter?s top value. in these cases the waveform generation mode (wgm03:0) bits must be set before the top value can be written to t he icr0 register. when writing the ic r0 register the high byte must be written to the icr0h i/o location before the low byte is written to icr0l. for more information on how to access the 16-bit registers refer to ?accessing 16-bit registers? on page 70 . 11.5.1 input capture trigger source the main trigger source for the input capture unit is the input capture pin (icp0). timer/counter0 can alternatively use the analog comparator output as trigger source for the input capture unit. the a nalog comparator is selected as trigger source by setting the analog comparator in put capture (acic) bit in ?acsr ? analog comparator con- trol and status register?. be aware that changing trig ger source can trigger a capt ure. the input capture flag must therefore be cleared after the change. both the input capture pin (icp0) and the analog comp arator output (aco) inputs are sampled using the same technique as for the t0 pin ( figure 11-3 on page 55 ). the edge detector is also identical. however, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increa ses the delay by four system icfn (int.req.) an a log comp a r a tor write icrn (16-bit regi s ter) icrnh ( 8 -bit) noi s e c a nceler icpn edge detector temp ( 8 -bit) data b u s ( 8 -bit) icrnl ( 8 -bit) tcntn (16-bit co u nter) tcntnh ( 8 -bit) tcntnl ( 8 -bit) acic* icnc ices aco* 58 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 clock cycles. note that the input of the noise canceler an d edge detector is always enabled unless the timer/coun- ter is set in a waveform generation mode that uses icr0 to define top. an input capture can be trigger ed by software by controlling the port of the icp0 pin. 11.5.2 noise canceler the noise canceler improves noise immunity by using a si mple digital filtering scheme. the noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. the noise canceler is enabled by setting the input capture noise canceler (icnc0) bit in timer/counter control register b (tccr0b). when enabled the noise canceler in troduces additional four system clock cycles of delay from a change applied to the input, to the update of th e icr0 register. the noise canceler uses the system clock and is therefore not affected by the prescaler. 11.5.3 using the input capture unit the main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming events. the time between two events is critical. if the processor has not read the captured value in the icr0 register before the next event o ccurs, the icr0 will be overwritten with a ne w value. in this case the result of the capture will be incorrect. when using the input capture interrupt, the icr0 register should be read as early in the interrupt handler routine as possible. even though the input capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. using the input capture unit in any mode of operation when the top value (resolution) is actively changed during operation, is not recommended. measurement of an external signal?s duty cycle requires that the trigger edge is changed after each capture. changing the edge sensing must be done as early as po ssible after the icr0 register has been read. after a change of the edge, the input capture flag (icf0) must be cleared by software (writing a logical one to the i/o bit location). for measuring frequency only, the clearing of the icf0 flag is not required (if an interrupt handler is used). 11.6 output compare units the 16-bit comparator continuously compares tcnt0 with the output compare register (ocr0x). if tcnt equals ocr0x the comparator signals a match. a match will set the output compar e flag (ocf0x) at the next timer clock cycle. if enabled (ocie0x = 1), the output compare flag generates an output compare interrupt. the ocf0x flag is automatically cleared when the interrupt is executed. al ternatively the ocf0x flag can be cleared by software by writing a logical one to its i/o bit location. the waveform generator uses the match signal to generate an output according to operating mode set by the waveform gener ation mode (wgm03:0) bits and compare output mode (com0x1:0) bits. the top and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation ( ?modes of operation? on page 61 ). a special feature of output compare unit a allows it to define the timer/counter top value (i.e., counter resolu- tion). in addition to the counter resolution, the top va lue defines the period time for waveforms generated by the waveform generator. figure 11-6 on page 59 shows a block diagram of the output compare unit. the small ?n? in the register and bit names indicates the device number (n = 0 for timer/counter 0), and the ?x? i ndicates output compare unit (a/b). the elements of the block diagram that are not directly a part of the output compare unit are gray shaded. 59 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 11-6. output compare unit, block diagram the ocr0x register is double buffered when using any of the twelve pulse width modulation (pwm) modes. for the normal and clear timer on compar e (ctc) modes of operation, the double buffering is di sabled. the double buffering synchronizes the update of the ocr0x compare re gister to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocr0x register access may seem complex, but this is not case. when the double buffering is enabled, the cpu has access to the ocr0x buffer regi ster, and if double buffering is di sabled the cpu will access the ocr0x directly. the content of the ocr0x (b uffer or compare) register is on ly changed by a wr ite operation (the timer/counter does not update this register automatically as the tcnt0 and icr0 register). therefore ocr0x is not read via the high byte temporary register (temp). however, it is a good practice to read the low byte first as when accessing other 16-bit registers. writing the ocr0x registers must be done via the temp register since the compare of all 16 bits is done continuously. the high byte (ocr0xh) has to be written first. when the high byte i/o location is written by the cpu, t he temp register will be updated by the value written. then when the low byte (ocr0xl) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the ocr0x buffer or ocr0x compare register in the same system clock cycle. for more information of how to acce ss the 16-bit registers refer to ?accessing 16-bit registers? on page 70 . 11.6.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (0x) bit. forcing compare match will not set the ocf0x flag or reload/clear the timer, but the oc0x pin will be updated as if a real compare match had occurred (the com 01:0 bits settings define whether the oc0x pin is set, cleared or toggled). ocfnx (int.req.) = (16-bit comp a r a tor ) ocrnx b u ffer (16-bit regi s ter) ocrnxh b u f. ( 8 -bit) ocnx temp ( 8 -bit) data b u s ( 8 -bit) ocrnxl b u f. ( 8 -bit) tcntn (16-bit co u nter) tcntnh ( 8 -bit) tcntnl ( 8 -bit) comnx1:0 wgmn3:0 ocrnx (16-bit regi s ter) ocrnxh ( 8 -bit) ocrnxl ( 8 -bit) w a veform gener a tor top bottom 60 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 11.6.2 compare match blocking by tcnt0 write all cpu writes to the tcnt0 register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. this feature allows ocr0x to be initialized to the same va lue as tcnt0 without trigger- ing an interrupt when the timer/counter clock is enabled. 11.6.3 using the output compare unit since writing tcnt0 in any mode of operation will bl ock all compare matches for on e timer clock cycle, there are risks involved when changing tcnt0 when using any of the output compare channels, independent of whether the timer/counter is running or not. if the value written to tcnt0 equals the ocr0x value, th e compare match will be missed, resulting in incorrect waveform generation. do not write the tcnt0 equal to top in pwm modes with variable top values. the compare match for the top will be ignored and the counter will continue to 0xffff. similarly, do not write the tcnt0 value equal to bottom when the counter is downcounting. the setup of the oc0x should be performed before setting the data direction register for the port pin to output. the easiest way of setting the oc0x value is to use the force output compare (0x) strobe bits in normal mode. the oc0x register keeps its value even when changing between waveform generation modes. be aware that the com0x1:0 bits are not double bu ffered together with the compare value. changing the com0x1:0 bits will take effect immediately. 11.7 compare match output unit the compare output mode (com0x1:0) bits have two function s. the waveform generator uses the com0x1:0 bits for defining the output compare (oc0x) state at the next compare match. secondly the com0x1:0 bits control the oc0x pin output source. figure 11-7 on page 61 shows a simplified schematic of the logic affected by the com0x1:0 bit setting. the i/o registers, i/o bits, and i/o pi ns in the figure are shown in bold. only the parts of the general i/o port control regi sters (ddr and port) that are affected by the com0x1:0 bi ts are shown. when refer- ring to the oc0x state, the reference is for the internal oc0x r egister, not the oc0x pin. if a system reset occur, the oc0x register is reset to ?0?. 61 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 11-7. compare match output unit, schematic (non-pwm mode) the general i/o port function is overridden by the outp ut compare (oc0x) from the waveform generator if either of the com0x1:0 bits are set. however, the oc0x pin direct ion (input or output) is still controlle d by the data direc- tion register (ddr) for the port pin. the data direction register bit for the oc0x pin (ddr_oc0x) must be set as output before the oc0x value is visibl e on the pin. the port override function is generally independent of the wave- form generation mode, but there are some exceptions. see table 11-2 on page 73 , table 11-3 on page 73 and table 11-4 on page 73 for details. the design of the output compare pin logic allows initia lization of the oc0x state before the output is enabled. note that some com0x1:0 bit settings are reserved for certain modes of operation. see ?register description? on page 72 the com0x1:0 bits have no effect on the input capture unit. 11.7.1 compare output mode and waveform generation the waveform generator uses the com0x1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the com0x1:0 = 0 tells the waveform generator that no action on the oc0x regist er is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 11-2 on page 73 . for fast pwm mode refer to table 11-3 on page 73 , and for phase correct and phase and frequency correct pwm refer to table 11-4 on page 73 . a change of the com0x1:0 bits state will have effect at the first compare matc h after the bits ar e written. for non- pwm modes, the action can be forced to have im mediate effect by using the 0x strobe bits. 11.8 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm03:0) and compare output mode (com0x1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the com0x1:0 bits control whether the pwm output generated should be inverted or not (inverted or non-inverted port ddr dq dq ocnx pin ocnx dq w a veform gener a tor comnx1 comnx0 0 1 data b u s focnx clk i/o 62 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 pwm). for non-pwm modes the com0x1:0 bits control whether the output should be set, cleared or toggle at a compare match ( ?compare match output unit? on page 60 ) for detailed timing in formation refer to ?timer/counter timing diagrams? on page 69 . 11.8.1 normal mode the simplest mode of operation is the normal mode (wgm03:0 = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply ov erruns when it passes its maximum 16-bit value (max = 0xffff) and then restarts from the bottom (0x0000). in normal operation the timer/coun- ter overflow flag (tov0) will be set in the same timer clock cy cle as the tcnt0 becomes zero. the tov0 flag in this case behaves like a 17th bit, except that it is only set, not cleared. ho wever, combined with the timer overflow interrupt that automatically clears t he tov0 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the input capture unit is easy to use in normal mode. ho wever, observe that the maximum interval between the external events must not exceed the reso lution of the counter. if the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. the output compare units can be used to generate interrupts at some given time. using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 11.8.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm03:0 = 4 or 12), the ocr0a or icr0 register are used to manipu- late the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcnt0) matches either the ocr0a (wgm03:0 = 4) or the icr0 (wgm03:0 = 12). the ocr0a or icr0 define the top value for the counter, hence also its resolution. this mode allows grea ter control of the compare match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in figure 11-8 on page 62 . the counter value (tcnt0) increases until a compare match occurs with either ocr0a or icr0, and then counter (tcnt0) is cleared. figure 11-8. ctc mode, timing diagram an interrupt can be generated at each time the counter value reaches the top value by either using the ocf0a or icf0 flag according to the register used to define the top value. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. howeve r, changing the top to a value close to bottom when the counter is running with none or a low prescaler va lue must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr0a or icr0 is lower than the current value of tcnt0, the counter will miss the compare match. the co unter will then have to co unt to its maximum value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. in many cases this feature is tcntn ocna (toggle) ocna interr u pt fl a g s et or icfn interr u pt fl a g s et (interr u pt on top) 1 4 period 2 3 (comna1:0 = 1) 63 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 not desirable. an alternative will then be to use the fast pwm mode using ocr0a for defining top (wgm03:0 = 15) since the ocr0a then will be double buffered. for generating a waveform output in ctc mode, the oc0a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com0a1:0 = 1). the oc0a value will not be visible on the port pin unless the data direction for th e pin is set to output (ddr_oc0a = 1). the waveform generated will have a ma ximum frequency of 0 a = f clk_i/o /2 when ocr0a is set to zero (0x0000). the waveform fre- quency is defined by the following equation: the n variable represents the prescaler factor (1, 8, 64, 256, or 1024). as for the normal mode of operation, the tov0 flag is set in the same timer clock cy cle that the counter counts from max to 0x0000. 11.8.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm03 :0 = 5, 6, 7, 14, or 15) provides a high frequency pwm waveform generation option. the fast pwm differs from the other pwm options by its single-slope operation. the counter counts from bottom to top then restarts from bottom. in non-inverting compare output mode, the output compare (oc0x) is cleared on the compar e match between tcnt0 and ocr0x, and set at bottom. in inverting compare output mode output is set on co mpare match and cleared at bottom. due to the single- slope operation, the operating frequency of the fast pw m mode can be twice as high as the phase correct and phase and frequency correct pwm modes that use dual-slope operation. this high frequency makes the fast pwm mode well suited for power regulation, rectification, and dac applic ations. high frequency a llows physically small sized external components (coils, capacito rs), hence reduces total system cost. the pwm resolution for fast pwm can be fixed to 8-, 9-, or 10-bit, or defined by either icr0 or ocr0a. the mini- mum resolution allowed is 2-bit (icr0 or ocr0a set to 0x0003), and the maximum resolution is 16-bit (icr0 or ocr0a set to max). the pwm resolu tion in bits can be calculated by using the following equation: in fast pwm mode the counter is incremented until the counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff (wgm03:0 = 5, 6, or 7), the value in icr0 (wgm03:0 = 14), or the value in ocr0a (wgm03:0 = 15). the counter is then cleared at the foll owing timer clock cycle. the timing diagram for the fast pwm mode is shown in figure 11-9 on page 64 . the figure shows fast pwm mode when ocr0a or icr0 is used to define top. the tcnt0 va lue is in the timing diagram shown as a histogram for illustrating the single-slope operation. the diagram includes non-inverted and invert ed pwm outputs. the small horizontal line marks on the tcnt0 slopes represent co mpare matches between ocr0x and tcnt0. the oc0x interrupt flag will be set when a compare match occurs. f ocna f clk_i/o 2 n 1 ocrna + ?? ?? --------------------------------------------------- = r fpwm top 1 + ?? log 2 ?? log ----------------------------------- = 64 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 11-9. fast pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each time the counter reaches top. in addition the oc0a or icf0 flag is set at the same timer clock cycle as tov0 is set when either ocr0a or icr0 is used for defining the top value. if one of the interrupts are enabled, the interrupt handler routine can be used for updating the top and com- pare values. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare regi sters. if the top value is lo wer than any of the compare registers, a compare match will never occur between the tcnt0 and the ocr0x. note that when using fixed top values the unused bits are masked to zero when any of the ocr0x registers are written. the procedure for updating icr0 differs from updating ocr0a when used for defining the top value. the icr0 register is not double buffered. this means that if icr0 is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new icr0 value writ ten is lower than the current value of tcnt0. the result will then be that the counter will mi ss the compare match at the top value. the counter will then have to count to the max value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. the ocr0a register however, is double buffered. this feature allows the ocr0 a i/o location to be written anytime. when the ocr0a i/o location is written the value written will be put into the ocr0a buffer register. the ocr0a compare register will then be updated with the value in the buffer register at the next timer clock cycle the tcnt0 matches top. the update is done at the same timer clock cycle as the tcnt0 is cleared and the tov0 flag is set. using the icr0 register for defining top works well w hen using fixed top values. by using icr0, the ocr0a register is free to be used for generating a pwm outp ut on oc0a. however, if the base pwm frequency is actively changed (by changing the top value), using the ocr0a as top is clearly a better choice due to its double buffer feature. in fast pwm mode, the compare units allow generation of pwm waveforms on the oc0x pins. setting the com0x1:0 bits to two will produce a non-inverted pwm and an inverted pwm ou tput can be gener ated by setting the com0x1:0 to three (see table 11-3 on page 73 ). the actual oc0x value will only be visible on the port pin if the data direction for the port pin is set as output (ddr_oc0x). the pw m waveform is generated by setting (or clearing) the oc0x register at the compare match betw een ocr0x and tcnt0, and clearing (or setting) the oc0x register at the timer clock cycle the co unter is cleared (changes from top to bottom). tcntn ocrnx/top update and tovn interrupt flag set and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 7 period 2 3 4 5 6 8 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) 65 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocr0x register represents s pecial cases when generating a pwm waveform output in the fast pwm mode. if the ocr0x is set equal to bottom (0x0000) the output will be a narrow spike for each top+1 timer clock cycle. setting the ocr0x equal to top will result in a constant high or low output (depending on the polarity of the output set by the com0x1:0 bits.) a frequency (with 50% duty cycle) wavefo rm output in fast pwm mode can be achieved by setting oc0a to toggle its logical level on each compare match (com0a1:0 = 1). th e waveform generated will have a maximum fre- quency of f 0 a = f clk_i/o /2 when ocr0a is set to zero (0x0000). this f eature is similar to the oc0a toggle in ctc mode, except the double buffer feature of the output compare unit is enabled in the fast pwm mode. 11.8.4 phase correct pwm mode the phase correct pulse width modulation or phase correc t pwm mode (wgm03:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is, like the phase and frequency correct pwm mode, based on a dual-slope operation. the counter counts repeatedly from bot- tom (0x0000) to top and then from top to bottom. in non-inverting compare output mode, the output compare (oc0x) is cleared on the compare match between tcnt0 and ocr0x while upcounting, and set on the compare match while downcounting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. the pwm resolution for the phase correct pwm mode can be fi xed to 8-, 9-, or 10-bit, or defined by either icr0 or ocr0a. the minimum resoluti on allowed is 2-bit (icr0 or ocr0a set to 0x0003), and the maximum resolution is 16-bit (icr0 or ocr0a set to max). the pwm resolution in bits can be calculated by using the following equation: in phase correct pwm mode the counter is incremented unt il the counter value matches either one of the fixed val- ues 0x00ff, 0x01ff, or 0x03ff (wgm03:0 = 1, 2, or 3) , the value in icr0 (wgm03:0 = 10), or the value in ocr0a (wgm03:0 = 11). the counter has then reached the top and changes the count direction. the tcnt0 value will be equal to top for one time r clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 11-10 on page 66 . the figure shows phase correct pwm mode when ocr0a or icr0 is used to define top. the tcnt0 value is in the timing diagram shown as a histogram for illu strating the dual-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt0 slopes represent compare matches between ocr0x and tcnt0. the oc0x inte rrupt flag will be se t when a compare match occurs. f ocnxpwm f clk_i/o n1top + ?? ? ----------------------------------- = r pcpwm top 1 + ?? log 2 ?? log ----------------------------------- = 66 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 11-10. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each time the counter reaches bottom. when either ocr0a or icr0 is used for defining the top value, the oc0a or icf0 flag is set accordingly at the same timer clock cycle as the ocr0x registers are updated with the double buffer va lue (at top). the interrupt flags can be used to gener- ate an interrupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare regi sters. if the top value is lo wer than any of the compare registers, a compare match will never occur between the tcnt0 and the ocr0x. note that when using fixed top values, the unused bits are masked to zero when any of the ocr0x register s are written. as the third period shown in figure 11-10 on page 66 illustrates, changing the top actively while the timer/counter is running in the phase correct mode can result in an unsymmetrical output. the reason for this can be found in the time of u pdate of the ocr0x register. since the ocr0x update occurs at top, the pwm period starts and ends at top. this implies that the length of the falling slope is determined by the previous top value, while th e length of the rising slope is determined by the new top value. when these two values differ the two slopes of the period will differ in length. the difference in length gives the unsymmetrical re sult on the output. it is recommended to use the phase and frequency correc t mode instead of the phase correct mode when chang- ing the top value while the timer/counter is running. when using a static top value there are practically no differences between the two modes of operation. in phase correct pwm mode, the compare units allow generation of pwm waveforms on the oc0x pins. setting the com0x1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by set- ting the com0x1:0 to three (see table 11-4 on page 73 ). the actual oc0x value will on ly be visible on the port pin if the data direction for the port pin is set as output (ddr_oc0x). the pwm waveform is generated by setting (or clearing) the oc0x register at t he compare match between ocr0x and tcnt0 when the counter increments, and clearing (or setting) the oc0x register at compare match between ocr0x and tcnt0 when the counter decre- ments. the pwm frequency for the output when using phase correct pwm can be calculated by the following equation: ocrnx/top update and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 2 3 4 tovn interrupt flag set (interrupt on bottom) tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) f ocnxpcpwm f clk_i/o 2ntop ?? ---------------------------- - = 67 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocr0x register represent sp ecial cases when generating a pwm waveform output in the phase correct pwm mode. if the ocr0x is set equal to bottom the output will be co ntinuously low and if set equal to top the output will be continuously high for non-inverted pwm mode. for inverted pwm the output will have the opposite logic values. 11.8.5 phase and frequency correct pwm mode the phase and frequency correct pulse width modulation, or phase and frequency correct pwm mode (wgm03:0 = 8 or 9) provides a high resolution phase and frequency correct pwm waveform generation option. the phase and frequency correct pwm mode is, like the phase correct pwm mode, based on a dual-slope operation. the counter counts repeatedly from bottom (0x0000) to to p and then from top to bottom. in non-inverting com- pare output mode, the output compare (oc0x) is cleared on the compare match between tcnt0 and ocr0x while upcounting, and set on the compare match while downcounting. in inverting compare output mode, the operation is inverted. the dual-slope operation gives a lower maximum operation frequency compared to the sin- gle-slope operation. however, due to the symmetric feature of the dual -slope pwm modes, these modes are preferred for motor control applications. the main difference between the phase correct, and the phase and frequency correct pwm mode is the time the ocr0x register is updated by the ocr0x buffer register, (see figure 11-10 on page 66 and figure 11-11 on page 68 ). the pwm resolution for the phase and frequency correct pwm mode can be defined by either icr0 or ocr0a. the minimum resolution allowed is 2-bit (icr0 or ocr0a set to 0x0003), and the maximum resolution is 16-bit (icr0 or ocr0a set to max). the pwm resolution in bits can be calculated using the following equation: in phase and frequency correct pwm mode the counter is incremented until the counter value matches either the value in icr0 (wgm03:0 = 8), or the value in ocr0a (wgm03:0 = 9). the counter has then reached the top and changes the count direction. the tcnt 0 value will be equal to top for one timer clock cycle. the timing diagram for the phase correct and frequency correct pwm mode is shown on figure 11-11 on page 68 . the figure shows phase and frequency correct pwm mode when ocr0a or icr0 is used to define top. the tcnt0 value is in the timing diagram shown as a histogram for illustrating t he dual-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line mark s on the tcnt0 slopes represent compare matches between ocr0x and tcnt0. the oc0x interrupt fl ag will be set when a compare match occurs. r pfcpwm top 1 + ?? log 2 ?? log ----------------------------------- = 68 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 11-11. phase and frequency correct pwm mode, timing diagram the timer/counter overflow flag (tov0) is set at the same timer clock cycle as the ocr0x registers are updated with the double buffer value (at bottom). when either ocr0 a or icr0 is used for defining the top value, the oc0a or icf0 flag set when tcnt0 has reached top. the interrupt flags can then be used to generate an inter- rupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare regi sters. if the top value is lo wer than any of the compare registers, a compare match will never occur between the tcnt0 and the ocr0x. as figure 11-11 on page 68 shows the output generated is, in contrast to the phase correct mode, symmetrical in all periods. since the ocr0x registers are updated at bottom, the length of the rising and t he falling slopes will always be equal. this gives symmetrical output pulses and is therefore frequency correct. using the icr0 register for defining top works well w hen using fixed top values. by using icr0, the ocr0a register is free to be used for generating a pwm outp ut on oc0a. however, if the base pwm frequency is actively changed by changing the top value, us ing the ocr0a as top is clearly a better choice due to its double buffer feature. in phase and frequency correct pwm mode, the compar e units allow generation of pwm waveforms on the oc0x pins. setting the com0x1:0 bits to two will produce a non-inve rted pwm and an inverted pwm output can be gen- erated by setting the com0x1:0 to three (see table 11-4 on page 73 ). the actual oc0x valu e will only be visible on the port pin if the data direction for the port pin is set as output (ddr_oc0x). the pwm waveform is generated by setting (or clearing) the oc0x register at the compare match between ocr0x and tcnt0 when the counter increments, and clearing (or setting) the oc0x register at compare match between ocr0x and tcnt0 when the counter decrements. the pwm frequency for the output when using phase and frequency correct pwm can be cal- culated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). ocrnx/top updateand tovn interrupt flag set (interrupt on bottom) ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 2 3 4 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) f ocnxpfcpwm f clk_i/o 2ntop ?? ---------------------------- - = 69 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 the extreme values for the ocr0x register represents s pecial cases when generating a pwm waveform output in the phase correct pwm mode. if the ocr0x is set equal to bottom the output will be co ntinuously low and if set equal to top the output will be set to high for non-inverted pw m mode. for inverted pwm th e output will have the opposite logic values. 11.9 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk t0 ) is therefore shown as a clock enable signal in the following figures. the figures in clude information on when interrupt flags are set, and when the ocr0x reg- ister is updated with the ocr0x buffer value (only for modes utilizing double buffering). figure 11-12 on page 69 shows a timing diagram for the setting of ocf0x. figure 11-12. timer/counter timing diagram, setting of ocf0x, no prescaling figure 11-13 on page 69 shows the same timing data, but with the prescaler enabled. figure 11-13. timer/counter timing diagram, setting of ocf0x, with prescaler (f clk_i/o /8) figure 11-14 on page 70 shows the count sequence close to top in various modes. when using phase and fre- quency correct pwm mode the ocr0x re gister is updated at bottom. the ti ming diagrams will be the same, but clk tn (clk i/o /1) ocfnx clk i/o ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) 70 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 top should be replaced by bottom, top-1 by bottom+1 and so on. the same renaming applies for modes that set the tov0 flag at bottom. figure 11-14. timer/counter timing diagram, no prescaling figure 11-15 on page 70 shows the same timing data, but with the prescaler enabled. figure 11-15. timer/counter timing dia gram, with prescaler (f clk_i/o /8) 11.10 accessing 16-bit registers the tcnt0, ocr0a/b, and icr0 are 16-bit registers that can be accessed by the avr cpu via the 8-bit data bus. the 16-bit register must be byte accessed using two read or write operations. each 16-b it timer has a single 8-bit register for temporary storing of the high byte of the 16 -bit access. the same temporary register is shared between all 16-bit registers within each 16-bit timer. accessing the lo w byte triggers the 16-bit read or write operation. when the low byte of a 16-bit register is written by the cpu, the high byte stored in the temporary register, and the low byte written are both copied into the 16-b it register in the same cl ock cycle. when the low byte of a 16-bit register is tovn (fpwm) and icfn (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk tn (clk i/o /1) clk i/o tovn (fpwm) and icf n (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) 71 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 read by the cpu, the high byte of the 16-bit register is copied into the temp orary register in the same clock cycle as the low byte is read. not all 16-bit accesses uses the te mporary register for the high byte. r eading the ocr0a/b 16-bit registers does not involve using the temporary register. to do a 16-bit write, the high byte must be written befo re the low byte. for a 16-bit read, the low byte must be read before the high byte. the following code example shows how to access the 16-bit timer registers assuming t hat no interrupts updates the temporary register. the same principle can be used directly for accessing the ocr0a/b and icr0 registers. note: see ?code examples? on page 5 . the code example returns the tcnt0 value in the r17:r16 register pair. it is important to notice that accessing 16-bit registers ar e atomic operations. if an interrupt occurs between the two instructions accessing the 16-bit register, and the interr upt code updates the temporary register by accessing the same or any other of th e 16-bit timer registers, then the result of the access ou tside the interrupt will be corrupted. therefore, when both the main code and the interrupt code update the temporary register, the main code must dis- able the interrupts during the 16-bit access. the following code example shows how to do an atomic re ad of the tcnt0 register contents. reading any of the ocr0a/b or icr0 registers can be done by using the same principle. note: see ?code examples? on page 5 . assembly code example ... ; set tcnt 0 to 0x01ff ldi r17,0x01 ldi r16,0xff out tcnt 0 h,r17 out tcnt 0 l,r16 ; read tcnt 0 into r17:r16 in r16,tcnt 0 l in r17,tcnt 0 h ... assembly code example tim16_readtcnt 0 : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcnt 0 into r17:r16 in r16,tcnt 0 l in r17,tcnt 0 h ; restore global interrupt flag out sreg,r18 ret 72 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 the code example returns the tcnt0 value in the r17:r16 register pair. the following code example shows how to do an atomic writ e of the tcnt0 register c ontents. writi ng any of the ocr0a/b or icr0 registers can be done by using the same principle. note: see ?code examples? on page 5 . the code example requires that the r17:r16 register pair contains the value to be written to tcnt0. 11.10.1 reusing the temporary high byte register if writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. howeve r, note that the same rule of atom ic operation describe d previously also applies in this case. 11.11 register description 11.11.1 tccr0a ? timer/counter0 control register a ? bits 7:6 ? com0a1:0: compare output mode for channel a ? bits 5:4 ? com0b1:0: compare output mode for channel b the com0a1:0 and com0b1:0 control the behaviour of output compare pins oc0a and oc0b, respectively. if one or both com0a1:0 bits are written to one, the oc0a output overrides the normal port functionality of the i/o pin it is connected to. similarly, if one or both com0b1:0 bit are written to one, the oc 0b output overrides the nor- mal port functionality of the i/o pin it is connected to. note, however, that the data direction register (ddr) bit corresponding to the oc0a or oc0b pin must be set in order to enable the output driver. assembly code example tim16_writetcnt 0 : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcnt 0 to r17:r16 out tcnt 0 h,r17 out tcnt 0 l,r16 ; restore global interrupt flag out sreg,r18 ret bit 7 6 5 4 3210 0x2e com0a1 com0a0 com0b1 com0b0 ? ? wgm01 wgm00 tccr0a read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 73 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 when oc0a or oc0b is connected to the pin, the func tion of com0x1:0 bits depends on the wgm03:0 bits. table 11-2 shows the com0x1:0 bit functionality when the wgm03: 0 bits are set to a normal or ctc (non-pwm) mode. table 11-3 shows the com0x1:0 bit functiona lity when the wgm03:0 bits are set to one of the fast pwm modes. note: 1. a special case occurs when ocr0a/ocr0b equals top and com0a1/com0b1 is set. in this case the compare match is ignored, but set or clear is done at bottom. see ?fast pwm mode? on page 63 for more details. table 11-4 shows the com0x1:0 bit functiona lity when the wgm03:0 bits are set to the phase correct or the phase and frequency correct, pwm mode. note: 1. a special case occurs when ocr0a/oc r0b equals top and com0a1/com0b1 is set. ?phase correct pwm mode? on page 65 for more details. ? bits 1:0 ? wgm01:0: waveform generation mode combined with wgm03:2 bits of tccr0b, these bits control the counting sequence of the counter, the source for maximum (top) counter value, and what type of waveform to generate. see table 11-5 . modes of operation sup- table 11-2. compare output in non-pwm modes com0a1/ com0b1 com0a0 com0b0 description 0 0 normal port operation: oc0a/oc0b disconnected 1 toggle oc0a/oc0b on compare match 1 0 clear (set low) oc0a/oc0b on compare match 1 set (high) oc0a/oc0b on compare match table 11-3. compare output in fast pwm modes com0a1/ com0b1 com0a0/ com0b0 description 0 0 normal port operation: oc0a/oc0b disconnected 1 wgm03 = 0: normal port operation, oc0a/oc0b disconnected wgm03 = 1: toggle oc0a on compare match, oc0b reserved 1 (1) 0 clear oc0a/oc0b on compare match set oc0a/oc0b at bottom (non-inverting mode) 1 set oc0a/oc0b on compare match clear oc0a/oc0b at bottom (inverting mode) table 11-4. compare output in phase correct and phase & frequency correct pwm modes com0a1/ com0b1 com0a0/ com0b0 description 0 0 normal port operation: oc0a/oc0b disconnected. 1 wgm03 = 0: normal port operation, oc0a/oc0b disconnected wgm03 = 1: toggle oc0a on compare match, oc0b reserved 1 (1) 0 counting up: clear oc0a/oc0b on compare match counting down: set oc0a/oc0b on compare match 1 counting up: set oc0a/oc0b on compare match counting down: clear oc0a/oc0b on compare match 74 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 ported by the timer/counter unit are: normal mode (counter), clear timer on compare match (ctc) mode, and three types of pulse width modulation (pwm) modes. ( ?modes of operation? on page 61 ). 11.11.2 tccr0b ? timer/counter0 control register b ? bit 7 ? icnc0: input capture noise canceler setting this bit (to one) activates the input capture noise canceler. when the noise canceler is activated, the input from the input capture pin (icp0) is filtered. the filter function requires four successive equal valued samples of the icp0 pin for changing its output. the input capture is therefore delayed by four oscillat or cycles when the noise canceler is enabled. ? bit 6 ? ices0: input capture edge select this bit selects which edge on the input capture pin (icp0) that is used to tr igger a capture event. when the ices0 bit is written to zero, a fallin g (negative) edge is used as trigger, and wh en the ices0 bit is written to one, a rising (positive) edge will trigger the capture. when a capture is triggered according to the ices0 setting , the counter value is copied into the input capture reg- ister (icr0). the event will also set the input ca pture flag (icf0), and this can be used to cause an input capture interrupt, if this interrupt is enabled. table 11-5. waveform generation modes mode wgm 0 3:0 mode of operation top update of ocr0 x at tov0 flag set on 0 0000 normal 0xffff immediate max 1 0001 pwm, phase correct, 8-bit 0x00ff top bottom 2 0010 pwm, phase correct, 9-bit 0x01ff top bottom 3 0011 pwm, phase correct, 10-bit 0x03ff top bottom 40100ctc ( clear timer on compare ) ocr0a immediate max 5 0101 fast pwm, 8-bit 0x00ff top top 6 0110 fast pwm, 9-bit 0x01ff top top 7 0111 fast pwm, 10-bit 0x03ff top top 8 1000 pwm, phase & freq. correct icr0 bottom bottom 9 1001 pwm, phase & freq. correct ocr0a bottom bottom 10 1010 pwm, phase correct icr0 top bottom 11 1011 pwm, phase correct ocr0a top bottom 12 1100 ctc ( clear timer on compare ) icr0 immediate max 13 1101 (reserved) ? ? ? 14 1110 fast pwm icr0 top top 15 1111 fast pwm ocr0a top top bit 7654 3210 0x2d icnc0 ices0 ? wgm03 wgm02 cs02 cs01 cs00 tccr0b read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 75 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 when the icr0 is used as top value (see description of the wgm03:0 bits located in the tccr0a and the tccr0b register), the icp0 is disconnected and co nsequently the input capt ure function is disabled. ? bit 5 ? reserved bit this bit is reserved for future use. for ensuring compatibili ty with future devices, this bit must be written to zero when tccr0b is written. ? bits 4:3 ? wgm03:2: waveform generation mode see ?tccr0a ? timer/counter0 control register a? on page 72 . ? bits 2:0 ? cs02:0: clock select the three clock select bits set the clock source to be used by the timer/counter, see figure 11-12 and figure 11- 13 . if external pin modes are used for the timer/counter0, transit ions on the t0 pin will clock the counter even if the pin is configured as an output. this featur e allows software cont rol of the counting. 11.11.3 tccr0c ? timer/counter0 control register c ? bit 7 ? foc0a: force output compare for channel a ? bit 6 ? foc0b: force output compare for channel b the foc0a/foc0b bits are only active when the wgm03: 0 bits specifies a non-pwm mode. however, for ensur- ing compatibility with future devices, these bits must be set to zero when tccr0a is written when operating in a pwm mode. when writing a logical one to the foc0a/foc0 b bit, an immediate compare match is forced on the waveform generation unit. the oc0a/oc0 b output is changed according to its com0x1:0 bits setting. note that the foc0a/foc0b bits are implemented as strobes. therefore it is the value present in the com0x1:0 bits that determine the effect of the forced compare. a foc0a/foc0b strobe will not generate any interrupt nor will it clear the ti mer in clear timer on compare match (ctc) mode using ocr0a as top. the foc0a/foc0b bits are always read as zero. table 11-6. clock select bit description cs02 cs01 cs00 description 0 0 0 no clock source (timer/counter stopped) 001clk i/o /1 (no prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on t0 pin. clock on falling edge 1 1 1 external clock source on t0 pin. clock on rising edge bit 7654 3210 0x2c foc0a foc0b ? ? ? ? ? ? tccr0c read/write w w r r r r r r initial value 0 0 0 0 0 0 0 0 76 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 ? bits 5:0 ? reserved bits these bits are reserved for fu ture use. for ensuring compat ibility with future devices, these bits must be written to zero when the regi ster is written. 11.11.4 tcnt0h and tcnt0l ? timer/counter0 the two timer/counter i/o locations (tcnt0h and tcnt0l, combined tcnt0) give direct access, both for read and for write operations, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary regi ster is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 70 . modifying the counter (tcnt0) while the counter is running introduces a risk of missing a compare match between tcnt0 and one of the ocr0x registers. writing to the tcnt0 register blocks (removes) the comp are match on the following timer clock for all compare units. 11.11.5 ocr0ah and ocr0al ? ou tput compare register 0 a 11.11.6 ocr0bh and ocr0bl ? ou tput compare register 0 b the output compare registers contain a 16-bit value t hat is continuously compared with the counter value (tcnt0). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc0x pin. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultane- ously when the cpu writes to these re gisters, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 70 . bit 76543210 0x29 tcnt0[15:8] tcnt0h 0x28 tcnt0[7:0] tcnt0l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x27 ocr1a[15:8] ocr0ah 0x26 ocr1a[7:0] ocr0al read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x25 ocr0b[15:8] ocr0bh 0x24 ocr0b[7:0] ocr0bl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 77 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 11.11.7 icr0h and icr0l ? input capture register 0 the input capture is updated with the counter (tcnt0) value each time an event occurs on the icp0 pin (or optionally on the analog comparator output for timer/counter0). the input capture can be used for defining the counter top value. the input capture register is 16-bit in size. to ensure that both the high and low bytes are read simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is sh ared by all the other 16-bit registers. ?accessing 16-bit registers? on page 70 . 11.11.8 timsk0 ? timer/counter interrupt mask register 0 ? bits 7:6, 4:3 ? reserved bits these bits are reserved for fu ture use. for ensuring compat ibility with future devices, these bits must be written to zero when the regi ster is written. ? bit 5 ? icie0: timer/counter0, input capture interrupt enable when this bit is written to one, and the i-flag in the st atus register is set (interrupts globally enabled), the timer/counter0 input capture interrupt is enabled. the corresponding interrupt vector (see ?interrupts? on page 66.) is executed when the icf0 flag, located in tifr0, is set. ? bit 2 ? ocie0b: timer/counter0, output compare b match interrupt enable when this bit is written to one, and the i-flag in the status register is set (int errupts globally enabled), the timer/counter0 output compare b match interrupt is enabled. the corresponding interrupt vector (see ?inter- rupts? on page 35 ) is executed when the ocf0b flag, located in tifr0, is set. ? bit 1 ? ocie0a: timer/counter0, output compare a match interrupt enable when this bit is written to one, and the i-flag in the status register is set (int errupts globally enabled), the timer/counter0 output compare a match interrupt is enabled. the corresponding interrupt vector (see ?inter- rupts? on page 35 ) is executed when the ocf0a flag, located in tifr0, is set. ? bit 0 ? toie0: timer/counter0, overflow interrupt enable when this bit is written to one, and the i-flag in the status register is set (int errupts globally enabled), the timer/counter0 overflow inte rrupt is enabled. the correspon ding interrupt vector (see ?interrupts? on page 35 ) is executed when the tov0 flag, located in tifr0, is set. bit 76543210 0x23 icr0[15:8] icr0h 0x22 icr0[7:0] icr0l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 7 6 5 4 3 2 1 0 0x2b ? ?icie0 ? ? ocie0b ocie0a toie0 timsk0 read/write r r r/w r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 78 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 11.11.9 tifr0 ? timer/counter interrupt flag register 0 ? bits 7:6, 4:3 ? reserved bits these bits are reserved for fu ture use. for ensuring compat ibility with future devices, these bits must be written to zero when the regi ster is written. ? bit 5 ? icf0: timer/counter0, input capture flag this flag is set when a capture event occurs on the icp0 pin. when the input capture register (icr0) is set by the wgm03:0 to be used as the top value, the icf0 fl ag is set when the counter reaches the top value. icf0 is automatically cleared when the input capture in terrupt vector is executed. alternatively, icf0 can be cleared by writing a logic one to its bit location. ? bit 2 ? ocf1b: timer/counter0, output compare b match flag this flag is set in the timer clock cycle after the coun ter (tcnt0) value matches the output compare register b (ocr0b). note that a forced output compare (0 b) strobe will not set the ocf0b flag. ocf1b is automatically cleared when the output compar e match b interrupt vector is executed. alternatively, ocf1b can be cleared by writing a logic one to its bit location. ? bit 1 ? ocf0a: timer/counter0, output compare a match flag this flag is set in the timer clock cycle after the coun ter (tcnt0) value matches the output compare register a (ocr0a). note that a forced output compare (1 a) strobe will not set the ocf0a flag. ocf0a is automatically cleared when the output compare match a interrupt vector is executed. alternatively, ocf0a can be cleared by writing a logic one to its bit location. ? bit 0 ? tov0: timer/c ounter0, overflow flag the setting of this flag is dependent of the wgm03:0 bits setting. in normal and ctc modes, the tov0 flag is set when the timer overflows. see table 11-5 on page 74 for the tov0 flag behavior when using another wgm03:0 bit setting. tov0 is automatically cleared when the timer/counter0 overflow interrupt vector is executed. alternatively, tov0 can be cleared by writing a logic one to its bit location. 11.11.10 gtccr ? general timer/counter control register ? bit 7 ? tsm: timer/counter synchronization mode writing the tsm bit to one activates the timer/counter synchronization mode. in this mode, the value that is writ- ten to the psr bit is kept, hence keeping the prescaler re set signal asserted. this ensures that the timer/counter bit 765432 1 0 0x2a ? ?icf0 ? ? ocf0b ocf0a tov0 tifr0 read/write r r r/w r r r/w r/w r/w initial value000000 0 0 bit 7 6 5 4 3 2 1 0 0x2f tsm ? ? ? ? ? ? psr gtccr read/write r/w r r r r r r r/w initial value 0 0 0 0 0 0 0 0 79 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 is halted and can be configured without the risk of advanc ing during configuration. wh en the tsm bit is written to zero, the psr bit is cleared by hardware , and the timer/coun ter start counting. ? bit 0 ? psr: prescaler 0 reset timer/counter 0 when this bit is one, the timer/count er0 prescaler will be reset. this bit is normally cleared im mediately by hard- ware, except if the tsm bit is set. 80 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 12. analog comparator the analog comparator compares the input values on the positive pin ain0 and negati ve pin ain1. when the volt- age on the positive pin ain0 is higher than the voltage on the negative pin ain1, the analog comparator output, aco, is set. the comparator can trigger a separate interrupt, exclusive to the analog comparator. the user can select interrupt triggering on comparator output rise, fall or toggle. a bloc k diagram of the comparator and its sur- rounding logic is shown in figure 12-1 . figure 12-1. analog comparator block diagram. see figure 1-1 on page 2 for pin use of analog comparator, and table 10-4 on page 49 and table 10-5 on page 50 for alternate pin usage. 12.1 register description 12.1.1 acsr ? analog comparator control and status register ? bit 7 ? acd: analog comparator disable when this bit is written logic one, the power to the analog co mparator is switched off. this bit can be set at any time to turn off the analog comparator, th us reducing power consumption in acti ve and idle mode. when changing the acd bit, the analog comparator interrupt must be disabled by clearing the acie bit in acsr. otherwise an inter- rupt can occur when the bit is changed. ? bits 6 ? res: reserved bit this bit is reserved and will always read zero. ? bit 5 ? aco: analog comparator output enables output of analog comparator. the output of the an alog comparator is synchronized and then directly con- nected to aco. the synchronization in troduces a delay of 1 - 2 clock cycles. bit 76543210 0x1f acd ? aco aci acie acic acis1 acis0 acsr read/write r/w r r r/w r/w r/w r/w r/w initial value00000000 81 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 ? bit 4 ? aci: analog comparator interrupt flag this bit is set by hardware when a comparator output event triggers the interrupt mode defined by acis1 and acis0. the analog comparator interrupt r outine is executed if the acie bit is set and the i-bit in sreg is set. aci is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, aci is cleared by writing a logic one to the flag. ? bit 3 ? acie: analog comparator interrupt enable when the acie bit is written logic one, the analog comparator interrupt request is enabled. when written logic zero, the interrupt request is disabled. ? bit 2 ? acic: analog comparator input capture enable when set, this bit enables the input capture function in timer/counter0 to be triggered by the analog comparator. in this case, the comparator output is directly connected to the input capture front-end logic, using the noise can- celer and edge select features of the timer/counter0 input capture interrupt. to make the comparator trigger the timer/counter0 input capture interrupt, the icie0 bit in ?timsk0 ? timer/counter inte rrupt mask register 0? must be set. when this bit is cleared, no connection between the a nalog comparator and the input capture function exists. ? bits 1:0 ? acis1, acis0: analog comparator interrupt mode select these bits determine which comparator events that trig ger the analog comparator interrupt. the different settings are shown in table 12-1 . when changing the acis1/acis0 bits, the analog comparator interrupt must be disabled by clearing its interrupt enable bit in ?acsr ? analog comparator control and status register?. otherwise an interrupt can occur when the bits are changed. 12.1.2 didr0 ? digital i nput disable register 0 ? bits 1:0 ? adc1d, adc0d: digital input disable when this bit is set, the digital input buffer on pin ain1 (adc1) / ain0 (adc0) is disabled and the corresponding pin register bit will read as zero. when used as an analog input but not requ ired as a digital input the power con- sumption in the digital input buffer can be reduced by writing this bit to logic one. table 12-1. selecting source for analog comparator interrupt. acis1 acis0 interrupt mode 0 0 comparator interrupt on output toggle. 01reserved 1 0 comparator interrupt on falling output edge. 1 1 comparator interrupt on rising output edge. bit 76543210 0x17 ? ? ? ? adc3d adc2d adc1d adc0d didr0 read/write r r r r r/w r/w r/w r/w initial value00000000 82 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 13. analog to digital converter 13.1 features ? 8-bit resolution ? 0.5 lsb integral non-linearity ? 1 lsb absolute accuracy ? 65s conversion time ? 15 ksps at full resolution ? four multiplexed single ended input channels ? input voltage range: 0 ? v cc ? supply voltage range: 2.5v ? 5.5v ? free running or single conversion mode ? adc start conversion by auto triggering on interrupt sources ? interrupt on adc conversion complete ? sleep mode noise canceler 13.2 overview attiny5/10 feature an 8-bit, successi ve approximation adc. the adc is connected to a 4-channel analog multi- plexer which allows four single-ended voltage inputs constr ucted from the pins of port b. the single-ended voltage inputs refer to 0v (gnd). the adc contains a sample-and-hold-circuit, which ensures that the input voltage to the adc is held at a constant level during conversion. a block diagram of the adc is shown in figure 13-1 on page 83 . internal reference voltage of v cc is provided on-chip. the adc is not available in attiny4/9. 13.3 operation in order to be able to use the adc the power reduction bi t, pradc, in the power redu ction register must be dis- abled. this is done by clearing the pradc bit. see ?prr ? power reduction register? on page 26 for more details. the adc is enabled by setting the adc enable bit, aden in ?adcsra ? adc control and status register a?. input channel selections will no t go into effect until aden is set. th e adc does not consume power when aden is cleared, so it is recommended to switch off t he adc before entering power saving sleep modes. the adc converts an analog input voltage to an 8-bit digital value using successive approximation. the minimum value represents gnd and the maximum value represents the voltage on v cc . the analog input channel is select ed by writing mux1:0 bits. see ?admux ? adc multiplexe r selection register? on page 92 . any of the adc input pins can be selected as single ended inputs to the adc. the adc generates an 8-bit result which is presented in the adc data register. see ?adcl ? adc data register? on page 94 . the adc has its own interrupt request which can be triggered when a conversion completes. 83 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 13-1. analog to digital converter block schematic 13.4 starting a conversion make sure the adc is powered by clearing the adc po wer reduction bit, pradc, in the power reduction regis- ter, prr (see ?prr ? power reduction register? on page 26 ). a single conversion is started by writing a logical one to the adc start conversion bit, adsc. this bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. if a differ- ent data channel is selected while a conv ersion is in progress, the adc will finish the current conversion before performing the channel change. alternatively, a conversion can be triggered automatically by various sources. auto triggering is enabled by setting the adc auto trigger enable bit, adate in adcsra. the trigger source is selected by setting the adc trigger select bits, adts in ?adcsrb ? adc control and status register b?. see table 13-4 on page 93 for a list of the trigger sources. when a positive edge occurs on the select ed trigger signal, the adc prescaler is reset and a con- version is started. this provides a method of starting conv ersions at fixed intervals. if the trigger signal still is set when the conversion completes, a new co nversion will not be started. if another positive edge occurs on the trigger signal during conversion, the edge will be i gnored. note that an inte rrupt flag will be set even if the specific interrupt is disabled. a conversion can thus be triggered without causing an interrupt. however, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. admux decoder 8-bit data bus mux1 mux0 adcsra adcl adps0 aden adps1 adps2 adate adif adsc trigger select vref adts2:0 start prescaler adc7:0 conversion logic 8-bit dac adcsrb - + adc3 adc2 adc1 adc0 v cc input mux interrupt flags adie adc irq sample & hold comparator channel 84 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 13-2. adc auto trigger logic using the adc interrupt flag as a trigger source makes the adc start a new conversi on as soon as the ongoing conversion has finished. the adc then operates in free running mode, co nstantly sampling and updating the adc data register. the first conversion mu st be started by writing a logical one to bit adsc bit in adcsra. in this mode the adc will perform su ccessive conversions independently of wh ether the adc interrupt flag, adif is cleared or not. if auto triggering is enabled, single conversions can be started by writing adsc in adcsra to one. adsc can also be used to determine if a conversion is in progres s. the adsc bit will be r ead as one duri ng a conversion, independently of how the conversion was started. 13.5 prescaling and conversion timing by default, the successive approximati on circuitry requires an input clock frequency between 50 khz and 200 khz to get maximum resolution. figure 13-3. adc prescaler the adc module contains a prescaler, as illustrated in figure 13-3 on page 84 , which generates an acceptable adc clock frequency from any cpu frequency above 100 kh z. the prescaling is set by the adps bits in adcsra. the prescaler starts counting from the moment the adc is switched on by setting t he aden bit in adcsra. the prescaler keeps running for as long as the aden bit is set, and is continuously reset when aden is low. adsc adif source 1 source n adts[2:0] conversion logic prescaler start clk adc . . . . edge detector adate 7-bit adc prescaler adc clock source ck adps0 adps1 adps2 ck/128 ck/2 ck/4 ck/8 ck/16 ck/32 ck/64 reset aden start 85 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 when initiating a single ended conversion by setting the adsc bit in adcsra, the conversion starts at the follow- ing rising edge of the adc clock cycle. a normal conversion takes 13 adc clock cycles, as summarised in table 13-1 on page 86 . the first conversion after the adc is switched on (aden in ad csra is set) takes 25 adc clock cycl es in order to initialize the analog circuitry. see figure 13-4 . figure 13-4. adc timing diagram, first conver sion (single conversion mode) the actual sample-and-hold takes place 3 adc clock cycles after the start of a normal conversion and 16 adc clock cycles after the start of a first conversion. see figure 13-5 . when a conversion is comp lete, the result is writ- ten to the adc data registers, and adif is set. in sing le conversion mode, adsc is cleared simultaneously. the software may then set adsc again, an d a new conversion will be initiated on the first rising adc clock edge. figure 13-5. adc timing diagram, single conversion when auto triggering is used, the prescaler is reset when the trigger event occurs. see figure 13-6 . this assures a fixed delay from the trigger event to the start of conversion. in this mode, the sample-and-hold takes place two adc clock cycles after t he rising edge on the trigger source signal. three additional cpu clock cycles are used for synchronization logic. conversion result adc clock adsc sample & hold adif adcl cycle number aden 1 212 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 first conversion next conversion 3 mux update mux update conversion complete 1 2 3 4 5 6 7 8 9 10 11 12 13 conversion result adc clock adsc adif adcl cycle number 12 one conversion next conversion 3 sample & hold mux update conversion complete mux update 86 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 13-6. adc timing diagram, auto triggered conversion in free running mode (see figure 13-7 ), a new conversion will be started immediately after the conversion com- pletes, while adsc remains high. figure 13-7. adc timing diagram, free running conversion for a summary of conversion times, see table 13-1 . table 13-1. adc conversion time condition sample & hold (cycles from start of conversion) conversion time (cycles) first conversion 16.5 25 normal conversions 3.5 13 auto triggered conversions 4 13.5 1 2 3 4 5 6 7 8 9 10 11 12 13 conversion result a dc clock t rigger s ource a dif a dcl c ycle number 12 one conversion next conversion conversion complete prescaler reset a date prescaler reset sample & hold mux update 11 12 13 conversion result adc clock adsc adif adcl cycle number 12 one conversion next conversion 34 conversion complete sample & hold mux update 87 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 13.6 changing channel the muxn bits in the admux register are single buffer ed through a temporary register to which the cpu has ran- dom access. this ensures that the channel selection only takes place at a safe point during the conversion. the channel is continuously updated until a conversion is st arted. once the conversion st arts, the channel selection is locked to ensure a sufficient sampling time for the adc. continuous upd ating resumes in the last adc clock cycle before the conversion completes (adif in adcsra is set). note that the conversion starts on the following rising adc clock edge after adsc is written. the user is t hus advised not to write new channel selection values to admux until one adc clock cycle after adsc is written. if auto triggering is used, the exact time of the triggerin g event can be indeterministic. special care must be taken when updating the admux register, in order to control which conversion w ill be affected by the new settings. if both adate and aden is written to one, an interrupt event can occur at any time. if the admux register is changed in this period, the user cannot tell if the next co nversion is based on the old or the new settings. admux can be safely updated in the following ways: ? when adate or aden is cleared. ? during conversion, minimum one adc clock cycle after the trigger event. ? after a conversion, before the interrupt flag used as trigger source is cleared. when updating admux in one of th ese conditions, the new settings will affect the next adc conversion. 13.6.1 adc input channels when changing channel selections, the user should observe the following guid elines to ensure that the correct channel is selected: ? in single conversion mode, always select the channel be fore starting the conversion. the channel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the conversion to complete before changing the channel selection. ? in free running mode, always select the channel before starting the first conversion. the channel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the first conversion to complete, and then change the channel selection. si nce the next conversion has already started automatically, the nex t result will reflect the previous channel selection. subsequent conversions will reflect the new channel selection. 13.6.2 adc voltage reference the reference voltage of the adc dete rmines the conversion range, which in this case is limited to 0v (v gnd ) and v ref = v cc . channels that exceed v ref will result in codes saturated at 0xff. 13.7 adc noise canceler the adc features a noise canceler that enables conversion during sleep m ode to reduce noise induced from the cpu core and other i/o peripherals. the noise canceler can be used with adc noise reduction and idle mode. to make use of this feature, the following procedure should be used: ? make sure that the adc is enabled and is not busy c onverting. single conversion mode must be selected and the adc conversion complete interrupt must be enabled. ? enter adc noise reduction mode (or idle mode). th e adc will start a conversion once the cpu has been halted. ? if no other interrupts occu r before the adc conversion completes, th e adc interrupt will wake up the cpu and execute the adc conversion complete interrupt routine. if another interrupt wakes up the cpu before the adc conversion is complete, that interr upt will be executed, and an adc conver sion complete inte rrupt request will 88 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 be generated when the adc conversion completes. the cpu will remain in active mode until a new sleep command is executed. note that the adc will not be automatically turned o ff when entering other sleep m odes than idle mode and adc noise reduction mode. the user is advised to write zero to aden before entering such sleep modes to avoid excessive power consumption. 13.8 analog input circuitry the analog input circuitry for singl e ended channels is illustrated in figure 13-8 an analog source applied to adcn is subjected to the pin capacitance and input leakage of t hat pin, regardless of whether that channel is selected as input for the adc. when the channel is selected, the source must drive the s/h (sample and hold) capacitor through the series resistance (combined resistance in the input path). figure 13-8. analog input circuitry the capacitor in figure 13-8 depicts the total capacitance, including t he sample/hold capacitor and any stray or parasitic capacitance inside the devi ce. the value given is worst case. the adc is optimized for analog signals wi th an output impedance of approximately 10 k ? , or less. with such sources, the sampling time will be negligible. if a source with higher impedance is us ed, the sampling time will depend on how long time the source needs to charge the s/ h capacitor. this can vary widely. the user is recom- mended to only use low impedance sources with slowly vary ing signals, since this mi nimizes the required charge transfer to the s/h capacitor. signal components higher than the nyquist frequency (f adc /2) should not be present to avoid distortion from unpre- dictable signal convolution. the user is advised to remove high frequency co mponents with a low-pass filter before applying the signals as inputs to the adc. 13.9 noise canceling techniques digital circuitry inside and outside the device generates emi which might affect the accuracy of analog measure- ments. when conversion accu racy is critical, the noise level can be reduced by applying the following techniques: ? keep analog signal paths as short as possible. ? make sure analog tracks run over the analog ground plane. ? keep analog tracks well away from high-speed switching digital tracks. ? if any port pin is used as a digital output, it mustn?t switch while a conversion is in progress. ? place bypass capacitors as close to v cc and gnd pins as possible. adcn i ih 1..100 k ohm c s/h = 14 pf v cc /2 i il 89 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 where high adc accuracy is required it is recommended to use adc noise reduction mode, as described in sec- tion 13.7 on page 87 . a good system design with properly placed, external bypass capacitors does reduce the need for using adc noise reduction mode 13.10 adc accuracy definitions an n-bit single-ended adc converts a voltage linearly between gnd and v ref in 2 n steps (lsbs). the lowest code is read as 0, and the highest code is read as 2 n -1. several parameters describe the deviation from the ideal behavior: ? offset: the deviation of the first transition (0x00 to 0x01) compared to the ideal transition (at 0.5 lsb). ideal value: 0 lsb. figure 13-9. offset error o u tp u t code v ref inp u t volt a ge ide a l adc act ua l adc off s et error 90 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 ? gain error: after adjusting for offset, the gain error is fo und as the deviation of the last transition (0xfe to 0xff) compared to the ideal transition (at 1.5 lsb below maximum). ideal value: 0 lsb figure 13-10. gain error ? integral non-linearity (inl): after adjusting for offset and gain error, the inl is the maximum deviation of an actual transition compared to an ideal transition for any code. ideal value: 0 lsb. figure 13-11. integral non- linearity (inl) ? differential non-linearity (dnl): the maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 lsb). ideal value: 0 lsb. o u tp u t code v ref inp u t volt a ge ide a l adc act ua l adc g a in error o u tp u t code v ref inp u t volt a ge ide a l adc act ua l adc inl 91 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 13-12. differential non-linearity (dnl) ? quantization error: due to the quantiz ation of the input voltage into a finite number of codes, a range of input voltages (1 lsb wide) will code to the same value. always 0.5 lsb. ? absolute accuracy: the maximum deviatio n of an actual (unadjusted) transiti on compared to an ideal transition for any code. this is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. ideal value: 0.5 lsb. 13.11 adc conversion result after the conversion is complete (adi f is high), the conversion result ca n be found in the adc data register (adcl). for single ended conversion, the result is where v in (see table 13-2 on page 92 ) is the voltage on the selected input pin and v cc is the voltage reference. 0x00 represents analog ground, and 0xff represents the selected reference voltage minus one lsb. output code 0xff 0x00 0 v ref input voltage dnl 1 lsb adcl v in 256 ? v cc ----------------------- = 92 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 13.12 register description 13.12.1 admux ? adc multiplexer se lection register ? bits 7:2 ? res: reserved bits these bits are reserved and will always read zero. ? bits 1:0 ? mux1:0: analog channel selection bits the value of these bits selects which combination of analog inputs are connected to the adc. see table 13-2 for details.. if these bits are changed during a conversion, the change will not go in effect until the conversion is complete (adif in adcsra is set) 13.12.2 adcsra ? adc control and status register a ? bit 7 ? aden: adc enable writing this bit to one enables the adc. by writing it to zero, th e adc is turned off. turning the adc off while a con- version is in progress, will terminate this conversion. ? bit 6 ? adsc: adc start conversion in single conversion mode, write this bit to one to start each conversion. in free running mode, write this bit to one to start the first conversion. the first conversion after adsc has been written after the adc has been enabled, or if adsc is written at the same ti me as the adc is enabled, will take 25 adc clock cycles in stead of the normal 13. this first conversion perf orms initializat ion of the adc. adsc will read as one as long as a conv ersion is in progress. when the conver sion is complete, it returns to zero. writing zero to this bit has no effect. ? bit 5 ? adate: adc auto trigger enable when this bit is written to one, auto triggering of the adc is en abled. the adc will start a conversion on a positive edge of the selected trigger signal. the trigger source is selected by setting the adc trigger select bits, adts in adcsrb. bit 76543210 0x1b ? ? ? ? ? ? mux1 mux0 admux read/write r r r r r r r/w r/w initial value00000000 table 13-2. input channel selections mux1 mux0 single ended input pin 0 0 adc0 pb0 1 adc1 pb1 1 0 adc2 pb2 1 adc3 pb3 bit 76543210 0x1d aden adsc adate adif adie adps2 adps1 adps0 adcsra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 93 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 ? bit 4 ? adif: adc interrupt flag this bit is set when an adc conversion completes and t he data registers are updated. the adc conversion com- plete interrupt is requested if the ad ie bit is set. adif is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, adif is cleared by writing a logical one to the flag. ? bit 3 ? adie: adc interrupt enable when this bit is written to one, the adc c onversion complete interrupt request is enabled. ? bits 2:0 ? adps2:0: adc prescaler select bits these bits determine the division factor between the system clock frequency and the input clock to the adc. 13.12.3 adcsrb ? adc control and status register b ? bits 7:3 ? res: reserved bits these bits are reserved and will always read zero. ? bits 2:0 ? adts2:0: adc auto trigger source if adate in adcsra is written to on e, the value of these bits selects wh ich source will trigger an adc conversion. if adate is cleared, the adts2:0 se ttings will have no effect. a conversion will be triggered by the rising edge of the selected interrupt flag. note that sw itching from a trigger source that is cl eared to a trigger source that is set, will generate a positive e dge on the trigger signal. if aden in adcsra is set, this will start a conversion. switching to free running mode (adts[2:0]=0) will not cause a trigger event, even if the adc interrupt flag is set . table 13-3. adc prescaler selections adps2 adps1 adps0 division factor 000 2 001 2 010 4 011 8 100 16 101 32 110 64 111 128 bit 76543210 0x1c ? ? ? ? ? adts2 adts1 adts0 adcsrb read/write r r r r r r/w r/w r/w initial value00000000 table 13-4. adc auto trigger source selections adts2 adts1 adts0 trigger source 0 0 0 free running mode 0 0 1 analog comparator 0 1 0 external interrupt flag 0 0 1 1 timer/counter 0 compare match a 94 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 13.12.4 adcl ? adc data register when an adc conversion is complete, the result is found in the adc register. ? bits 7:0 ? adc7:0: adc conversion result these bits represent the result from the conversion. 13.12.5 didr0 ? digital input disable register 0 ? bits 7:4 ? res: reserved bit these bits are reserved and will always read zero. ? bits 3:0 ? adc3d..adc0d: ad c3..0 digital input disable when this bit is written logic one, the digital input bu ffer on the corresponding adc pin is disabled. the corre- sponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to the adc3..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 1 0 0 timer/counter 0 overflow 1 0 1 timer/counter 0 compare match b 1 1 0 pin change interrupt 0 request 1 1 1 timer/counter 0 capture event table 13-4. adc auto trigger source selections adts2 adts1 adts0 trigger source bit 76543210 0x19 adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl read/writerrrrrrrr initial value00000000 bit 765432 1 0 0x17 ? ? ? ? adc3d adc2d adc1d adc0d didr0 read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 95 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 14. programming interface 14.1 features ? physical layer: ? synchronous data transfer ? bi-directional, half-duplex receiver and transmitter ? fixed frame format with one start bit, 8 data bits, one parity bit and 2 stop bits ? parity error detection, frame error detection and break character detection ? parity generation and collision detection ? automatic guard time insertion between data reception and transmission ? access layer: ? communication based on messages ? automatic exception handling mechanism ? compact instruction set ? nvm programming access control ? tiny programming interface control and status space access control ? data space access control 14.2 overview the tiny programming interface (tpi) supports external programming of all non-volatile memories (nvm). mem- ory programming is done via the nvm controller, by executing nvm controller commands as described in ?memory programming? on page 106 . the tiny programming interface (tpi) pr ovides access to the programming facilit ies. the interface consists of two layers: the access layer and the physical layer. the layers are illustrated in figure 14-1 . figure 14-1. the tiny programming interface and related internal interfaces programming is done via the phys ical interface. this is a 3-pin interface, which uses the reset pin as enable, the tpiclk pin as the clock input, and the tpidata pin as data input and output. nvm can be programmed at 5v, only. 14.3 physical layer of tiny programming interface the tpi physical layer handles the basi c low-level serial communication. the tpi physical layer uses a bi-direc- tional, half-duplex serial receiver and transmitter. the ph ysical layer includes serial-to- parallel and parallel-to-serial data conversion, start-of-frame detec tion, frame error detection, parity e rror detection, parity generation and colli- sion detection. access layer physical layer nvm controller non-volatile memories tpiclk reset t pidata tiny programming interface (tpi) data bus 96 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 the tpi is accessed via three pins, as follows: reset : tiny programming interface enable input tpiclk: tiny programming interface clock input tpidata: tiny programming interface data input/output in addition, the v cc and gnd pins must be connected between the external programmer and the device. see fig- ure 14-2 . figure 14-2. using an external programmer for in-system programming via tpi nvm can be programmed at 5v, only. in some designs it may be necessary to protect components that can not tol- erate 5v with, for exam ple, series resistors. 14.3.1 enabling the following sequence enables the tiny programming interface (see figure 14-3 for guidance): ? apply 5v between v cc and gnd ? depending on the method of reset to be used: ? either: wait t tout (see table 16-4 on page 118 ) and then set the reset pin low. this will reset the device and enable the tpi physical layer. the reset pin must then be kept low for the entire programming session ? or: if the rstdisbl configuration bit has been programmed, apply 12v to the reset pin. the reset pin must be kept at 12v for the entire programming session ?wait t rst (see table 16-4 on page 118 ) ? keep the tpidata pin high for 16 tpiclk cycles figure 14-3. sequence for enabling the tiny programming interface attiny4/5/9/10 tpidata/pb0 gnd tpiclk/pb1 pb3/reset v cc pb2 tpi conn application +5v reset t rst tpidata tpiclk 16 x tpiclk cycles 97 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 14.3.2 disabling provided that the nvm enable bit has been cleared, the tpi is automatically disabled if the reset pin is released to inactive high state or, alternatively, if v hv is no longer ap plied to the reset pin. if the nvm enable bit is not cleared a power down is required to exit tpi programming mode. see nvmen bit in ?tpisr ? tiny programming interface status register? on page 105 . 14.3.3 frame format the tpi physical layer supports a fixed frame format. a fr ame consists of one character, eight bits in length, and one start bit, a parity bit and two stop bits. data is transferred with the le ast significant bit first. figure 14-4. serial frame format. symbols used in figure 14-4 : st: start bit (always low) d0-d7: data bits (least significant bit sent first) p: parity bit (using even parity) sp1: stop bit 1 (always high) sp2: stop bit 2 (always high) 14.3.4 parity bit calculation the parity bit is always calculated usi ng even parity. the value of the bit is calculated by doing an exclusive-or of all the data bits, as follows: p = d0 ? d1 ? d2 ? d3 ? d4 ? d5 ? d6 ? d7 ? 0 where: p: parity bit using even parity d0-d7: data bits of the character 14.3.5 supported characters the break character is equal to a 12 bit long low level. it can be extended beyond a bit-length of 12. figure 14-5. supported characters. 14.3.6 operation the tpi physical layer operates synchronously on the tpic lk provided by the exter nal programmer. the depen- dency between the clock edges and data sampling or data change is shown in figure 14-6 . data is changed at falling edges and samp led at rising edges. tpidata tpiclk sp1 st sp2 idle/st idle p d1 d0 d7 idle/st idle break character data character sp1 st sp2 idle/st idle p d1 d0 d7 tpidata tpidata 98 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 14-6. data changing and data sampling. the tpi physical layer supports two modes of operation: transmit and receive. by default, the layer is in receive mode, waiting for a start bit. the mode of operation is controlled by the access layer. 14.3.7 serial da ta reception when the tpi physical layer is in rece ive mode, data reception is started as soon as a st art bit has been detected. each bit that follows the start bit will be sampled at the rising edge of the tpic lk and shifted into the shift register until the second stop bit has been receiv ed. when the complete frame is presen t in the shift register the received data will be available fo r the tpi access layer. there are three possible exceptions in the receive mode: frame error, parity error and break detection. all these exceptions are signalized to the tpi a ccess layer, which then enters the error state and puts the tpi physical layer into receive mode, wait ing for a break character. ? frame error exception. the frame error exception indicate s the state of the stop bit. the frame error exception is set if the stop bit was read as zero. ? parity error exception. the parity of the data bits is calculated during the frame reception. after the frame is received completely, the result is compared with the parity bit of the fr ame. if the comparison fails the parity error exception is signalized. ? break detection exception. the break detection except ion is given when a complete frame of all zeros has been received. 14.3.8 serial data transmission when the tpi physical layer is ready to send a new frame it initiates data transmission by loading the shift register with the data to be transmitted. when the shift register has been loaded with new data, the transmitter shifts one complete frame out on the tpidata line at the transfer rate given by tpiclk. if a collision is detected during transmis sion, the output driver is disabled. the tp i access layer enters the error state and the tpi physical la yer is put into receive mode , waiting for a break character. 14.3.9 collision de tection exception the tpi physical layer uses one bi-directional data line for both data reception and transmission. a possible drive contention may occur, if the external programmer and the tpi physical layer drive the tpidata line simultane- ously. in order to reduce the effect of the drive contention, a collision de tection mechanism is supported. the collision detection is based on the way the tpi physical layer drives the tpidata line. the tpidata line is driven by a tri-state, push-pull driver with inte rnal pull-up. the output driver is always enabled when a logical zero is sent. when sendin g successive logical ones, the output is only driven actively during the first clock cycle. after this, the output driver is automatically tri-stat ed and the tpidata line is kept high by the internal pull-up. the output is re-enabled, when the next logical zero is sent. tpidata tpiclk sample setup 99 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 the collision detection is enab led in transmit mode, when the output dr iver has been disabl ed. the data line should now be kept high by the internal pull-up and it is monitored to see, if it is driven low by the external programmer. if the output is read low, a collision has been detected. there are some po tential pit-falls related to the way collision detection is performed . for example, collisions cannot be detected when the tpi physical layer transmits a bit-stream of successive logical zeros, or bit-stream of alter- nating logical ones and zeros. this is because the output dr iver is active all the time, preventing polling of the tpidata line. however, within a single frame the two stop bits should always be transmitted as logical ones, enabling collision detection at least once per frame (as long as the frame format is not viol ated regarding the stop bits). the tpi physical layer will cease transmi ssion when it detects a collision on the tpidata line. the collision is sig- nalized to the tpi access layer, which immediately c hanges the physical layer to receive mode and goes to the error state. the tpi access layer can be recovered from the error stat e only by sending a break character. 14.3.10 direction change in order to ensure correct timing of the half-duplex operation, a simple guard time mechanism has been added to the physical layer. when the tpi physical layer changes fr om receive to transmit mode, a configurable number of additional idle bits are inserted before the start bit is transmitted. the minimum tran sition time between receive and transmit mode is two idle bits. the total idle ti me is the specified guard time plus two idle bits. the guard time is configured by dedicated bits in the tpip cr register. the default guard time value after the phys- ical layer is initialized is 128 bits. the external programmer looses control of the tpidat a line when the tpi target changes from receive mode to transmit. the guard time feature relaxes this critical phase of the communication. when the external programmer changes from receive mode to transmit, a minimum of one idle bit should be inserted before the start bit is transmitted. 14.4 access layer of tiny programming interface the tpi access layer is responsible for handling the co mmunication with the external programmer. the communi- cation is based on message format, where each message comprises an instruction followed by one or more byte- sized operands. the instruction is always sent by the external programmer but operands are sent either by the external programmer or by the tpi access layer, depending on the type of instruction issued. the tpi access layer controls the character transfer direction on the tpi physical layer. it also handles the recov- ery from the error state after exception. the control and status space (css) of the tiny programming interface is allocated for co ntrol and status registers in the tpi access layer. the css consis t of registers directly involved in t he operation of the tpi itself. these reg- ister are accessible using the sldcs and sstcs instructions. the access layer can also access the data space, either directly or indirect ly using the pointer register (pr) as the address pointer. the data space is accessible using the sld, sst, sin and sout instructions. the address pointer can be stored in the pointer register using the sldpr instruction. 14.4.1 message format each message comprises an inst ruction followed by one or more byte op erands. the instructio n is always sent by the external programmer. depending on the instruction a ll the following operands are sent either by the external programmer or by the tpi. the messages can be categori zed in two types based on the instruction, as follows: ? write messages. a write message is a request to write data. the write message is sent entirely by the external programmer. this message type is used with th e sstcs, sst, stpr, sout and skey instructions. 100 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 ? read messages. a read message is a request to read data. the tpi reacts to the request by sending the byte operands. this message type is used wi th the sldcs, sld an d sin instructions. all the instructions except the skey in struction require the instruction to be followed by one byte operand. the skey instruction requires 8 byte operands. for more information, see the tpi instruction set on page 100 . 14.4.2 exception handling and synchronisation several situations are considered exceptions from normal operation of the tpi. when the tpi physical layer is in receive mode, these exceptions are: ? the tpi physical layer detects a parity error. ? the tpi physical layer detects a frame error. ? the tpi physical layer re cognizes a br eak character. when the tpi physical layer is in transmit mode, the possible exceptions are: ? the tpi physical layer detects a data collision. all these exceptions are signalized to the tpi access layer. the access layer responds to an exception by aborting any on-going operation and enters the error state. the access layer will stay in the error state unt il a break char- acter has been received, after which it is taken back to its default state. as a consequence, the external programmer can always synchro nize the protocol by si mply transmitting two succ essive break characters. 14.5 instruction set the tpi has a compact instruction set that is used to access the tpi control and status space (css) and the data space. the instructions allow the external programmer to access the tpi, the nvm controller and the nvm memo- ries. all instruct ions except skey require one byte operand following the instruct ion. the skey instruction is followed by 8 data bytes. all instructions are byte-sized. the tpi instruction set is summarised in table 14-1 . table 14-1. instruction set summary mnemonic operand description operation sld data, pr serial load from data space using indirect addressing data ? ds[pr] sld data, pr+ serial load from data space using indirect addressing and post-increment data ? ds[pr] pr ? pr+1 sst pr, data serial store to data space using indirect addressing ds[pr] ? data sst pr+, data serial store to data space using indirect addressing and post-increment ds[pr] ? data pr ? pr+1 sstpr pr, a serial store to pointer register using direct addressing pr[a] ? data sin data, a serial in from data space data ? i/o[a] sout a, data serial out to data space i/o[a] ? data 101 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 14.5.1 sld - serial load from data space using indirect addressing the sld instruction uses indirect addre ssing to load data from the data spac e to the tpi physical layer shift-regis- ter for serial read-out. the data space location is point ed by the pointer register (pr), where the address must have been stored before data is accessed. the pointer regi ster is either left unchanged by the operation, or post- incremented, as shown in table 14-2 . 14.5.2 sst - serial store to data space using indirect addressing the sst instruction uses indirect addressing to store into da ta space the byte that is sh ifted into the physical layer shift register. the data space location is pointed by the pointer register (pr), where the address must have been stored before the operation. the pointer register can be either left unchanged by the operation, or it can be post- incremented, as shown in table 14-3 . 14.5.3 sstpr - serial store to pointer register the sstpr instruction stores the data byte that is shifted into the physical layer shift register to the pointer regis- ter (pr). the address bit of the instruction specifies whic h byte of the pointer register is accessed, as shown in table 14-4 . sldcs data, a serial load from control and status space using direct addressing data ? css[a] sstcs a, data serial store to control and status space using direct addressing css[a] ? data skey key, {8{data}} serial key key ? {8{data}} table 14-1. instruction set summary (continued) mnemonic operand description operation table 14-2. the serial load from data space (sld) instruction operation opcode remarks register data ? ds[pr] 0010 0000 pr ? pr unchanged data ? ds[pr] 0010 0100 pr ? pr + 1 post increment table 14-3. the serial store to data space (sld) instruction operation opcode remarks register ds[pr] ?? data 0110 0000 pr ? pr unchanged ds[pr] ?? data 0110 0100 pr ? pr + 1 post increment table 14-4. the serial store to pointer register (sstpr) instruction operation opcode remarks pr[a] ?? data 0110 100a bit ?a? addresses pointer register byte 102 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 14.5.4 sin - serial in from i/o space using direct addressing the sin instruction loads data byte from the i/o space to the shift register of the physical layer for serial read-out. the instuction uses direct ad dressing, the address consisting of the 6 address bits of t he instruction, as shown in table 14-5 . 14.5.5 sout - serial out to i/o space using direct addressing the sout instruction stores the data byte that is shifted into the physical laye r shift register to the i/o space. the instruction uses direct addressing, the address consisting of the 6 address bi ts of the instruction, as shown in table 14-6 . 14.5.6 sldcs - serial load data from control and status space using direct addressing the sldcs instruction loads data byte from the tpi contro l and status space to the tp i physical layer shift regis- ter for serial read-out. the sldcs instruction uses di rect addressing, the direct address consisting of the 4 address bits of the instruction, as shown in table 14-7 . 14.5.7 sstcs - serial store data to control and status space using direct addressing the sstcs instruction stores the data byte that is shifted into the tpi physical layer shift register to the tpi control and status space. the sstcs instruction uses direct addressing, the direct address consisting of the 4 address bits of the instruction, as shown in table 14-8 . table 14-5. the serial in from i/o space (sin) instruction operation opcode remarks data ?? i/o[a] 0aa1 aaaa bits marked ?a? form the direct, 6-bit addres table 14-6. the serial out to i/o space (sout) instruction operation opcode remarks i/o[a] ?? data 1aa1 aaaa bits marked ?a? form the direct, 6-bit addres table 14-7. the serial load data from control and status space (sldcs) instruction operation opcode remarks data ?? css[a] 1000 aaaa bits marked ?a? form the direct, 4-bit addres table 14-8. the serial store data to control and status space (sstcs) instruction operation opcode remarks css[a] ?? data 1100 aaaa bits marked ?a? form the direct, 4-bit addres 103 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 14.5.8 skey - serial key signaling the skey instruction is used to sign al the activation key t hat enables nvm programming . the skey instruction is followed by the 8 data bytes that includ es the activation key, as shown in table 14-9 . 14.6 accessing the non-volati le memory controller by default, nvm programming is not enabled. in order to access the nvm controller and be able to program the non-volatile memories, a unique key mu st be sent using the skey instruction. the 64-bit key that will enable nvm programming is given in table 14-10 . after the key has been given, the non-volatile memory en able (nvmen) bit in the tp i status register (tpisr) must be polled until the non-volatile memory has been enabled. nvm programming is disabled by writing a logical zero to the nvmen bit in tpisr. 14.7 control and status sp ace register descriptions the control and status registers of the tiny programming interface are mapped in the control and status space (css) of the interface. these regist ers are not part of the i/o register map and are accessible via sldcs and sstcs instructions, only. the control an d status registers are directly involved in configuration and status monitor- ing of the tpi. a summary of css registers is shown in table 14-11 . table 14-9. the serial key signaling (skey) instruction operation opcode remarks key ?? {8[data}} 1110 0000 data bytes follow after instruction table 14-10. enable key for non-volatile memory programming key value nvm program enable 0x1289ab45cdd888ff table 14-11. summary of control and status registers addr. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0f tpiir tiny programming interface identification code 0x0e ... 0x03 reserved ? ? ? ? ? ? ? ? 0x02 tpipcr ? ? ? ? ? gt2 gt1 gt0 0x01 reserved ? ? ? ? ? ? ? ? 0x00 tpisr ? ? ? ? ? ? nvmen ? 104 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 14.7.1 tpiir ? tiny programming in terface identification register ? bits 7:0 ? tpiic: tiny programming interface identification code these bits give the identification code for the tiny programming interfac e. the code can be used be the external programmer to identify the tpi. the identification code of the tiny programming interface is shown in table 14-12 .. 14.7.2 tpipcr ? tiny programming interface physical layer control register ? bits 7:3 ? res: reserved bits these bits are reserved and will always read zero. ? bits 2:0 ? gt[2:0]: guard time these bits specify the number of addition al idle bits that are inserted to the idle time when changing from recep- tion mode to transmission mode. addi tional delays are not inserted w hen changing from transmission mode to reception. the total idle time when changing from reception to tr ansmission mode is guard time plus two idle bits. table 14-13 shows the available guard time settings. the default guard time is 128 idle bits. to speed up the communication, the guard time should be set to the shortest safe value. bit 76543210 css: 0x0f programming interface identification code tpiir read/writerrrrrrrr initial value00000000 table 14-12. identification code for tiny programming interface code value interface identification 0x80 bit 76543210 css: 0x02 ? ? ? ? ? gt2 gt1 gt0 tpipcr read/writerrrrrr/wr/wr/w initial value00000000 table 14-13. guard time settings gt2 gt1 gt0 guard time (number of idle bits) 0 0 0 +128 (default value) 001+64 010+32 011+16 100+8 101+4 110+2 111+0 105 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 14.7.3 tpisr ? tiny programming interface status register ? bits 7:2, 0 ? res: reserved bits these bits are reserved and will always read zero. ? bit 1 ? nvmen: non-volatile memory programming enabled nvm programming is enabled when this bit is set. the exte rnal programmer can poll this bit to verify the interface has been successfully enabled. nvm programming is disabled by writing this bit to zero. bit 76543210 css: 0x00 ? ? ? ? ? ? nvmen ? tpipcr read/writerrrrrrr/wr initial value00000000 106 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 15. memory programming 15.1 features ? two embedded non-volatile memories: ? non-volatile memory lock bits (nvm lock bits) ? flash memory ? four separate sections inside flash memory: ? code section (program memory) ? signature section ? configuration section ? calibration section ? read access to all non-volatile me mories from application software ? read and write access to non-volatile memories from external programmer: ? read access to all non-volatile memories ? write access to nvm lock bits, flash code section and flash configuration section ? external programming: ? support for in-system and mass production programming ? programming through the tiny programming interface (tpi) ? high security wi th nvm lock bits 15.2 overview the non-volatile memory (nvm) controller manages all a ccess to the non-volatile me mories. the nvm controller controls all nvm timing and access privile ges, and holds the st atus of the nvm. during normal execution the cpu will exec ute code from the code section of the flash memory (program memory). when entering sleep and no programming operations are ac tive, the flash memory is disabled to minimize power consumption. all nvm are mapped to the data memory. application so ftware can read the nvm from the mapped locations of data memory using load instruction with indirect addressing. the nvm has only one read port and, therefore, the next instruction and the data can not be read simultaneously. when the application reads data from nvm locations mapped to the data space, the data is read first before the next instruction is fetched. the cpu executio n is here delayed by one system clock cycle. internal programming operations to nvm have been dis abled and the nvm therefore appears to the application software as read-only. internal write or erase operations of the nvm will not be successful. the method used by the external programmer for writing the non-volatile memories is referred to as external pro- gramming. external programming can be done both in-system or in mass production. see figure 14-2 on page 96 . the external programmer can read and program th e nvm via the tiny programming interface (tpi). in the external programming mode all nvm can be read and programmed, except the signature and the calibration sections which are read-only. nvm can be programmed at 5v, only. 15.3 non-volatile memories the attiny4/5/9/10 have the following, embedded nvm: ? non-volatile memory lock bits ? flash memory with fo ur separate sections 107 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 15.3.1 non-volatile memory lock bits the attiny4/5/9/10 provide tw o lock bits, as shown in table 15-1 . the lock bits can be left unprogrammed ("1") or can be programmed ("0") to obtain the additional security shown in table 15-2 . lock bits can be erased to "1" with the chip erase command, only. notes: 1. program the configuration section bits before programming nvlb1 and nvlb2. 2. "1" means unprogrammed, "0" means programmed 15.3.2 flash memory the embedded flash memory of attiny4/5/9/10 has four separate sections, as shown in table 15-3 and table 15- 3 . table 15-1. lock bit byte lock bit bit no description default value 7 1 (unprogrammed) 6 1 (unprogrammed) 5 1 (unprogrammed) 4 1 (unprogrammed) 3 1 (unprogrammed) 2 1 (unprogrammed) nvlb2 1 non-volatile lock bit 1 (unprogrammed) nvlb1 0 non-volatile lock bit 1 (unprogrammed) table 15-2. lock bit protection modes memory lock bits (1) protection type lock mode nvlb2 (2) nvlb1 (2) 1 1 1 no memory lock feature enabled 210 further programming of the fl ash memory is disabled in the external programming mode. the configuration section bits are locked in the external programming mode 300 further programming and verification of the flash is disabled in the external programming mode. the configuration section bits are locked in the external programming mode table 15-3. number of words and pages in the flash (attiny9/10) section size (bytes) page size (words) pages waddr paddr code (program memory) 1024 8 64 [3:1] [9:4] configuration 8 8 1 [3:1] ? signature (1) 16 8 2 [3:1] [4:4] calibration (1) 8 8 1 [3:1] ? 108 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 notes: 1. this section is read-only. notes: 1. this section is read-only. 15.3.3 configuration section attiny4/5/9/10 have one configur ation byte, which resides in the configuration section. see table 15-5 . table 15-6 briefly describes the func tionality of all configuration bits and how they are mapped into the configura- tion byte. configuration bits are not affected by a chip erase but they can be cleared using the configuration section erase command (see ?erasing the configurat ion section? on page 112 ). note that configuratio n bits are locked if non- volatile lock bit 1 (nvlb1) is programmed. 15.3.3.1 latching of configuration bits all configuration bits are latched either when the device is reset or when the device exits the external programming mode. changes to configuration bit val ues have no effect until the device l eaves the external programming mode. table 15-4. number of words and pages in the flash (attiny4/5) section size (bytes) page size (words) pages waddr paddr code (program memory) 512 8 32 [3:1] [9:4] configuration 8 8 1 [3:1] ? signature (1) 16 8 2 [3:1] [4:4] calibration (1) 8 8 1 [3:1] ? table 15-5. configuration bytes configuration word address configuration word data high byte low byte 0x00 reserved configuration byte 0 0x01 ... 0x07 reserved reserved table 15-6. configuration byte 0 bit bit name description default value 7:3 ? reserved 1 (unprogrammed) 2 ckout system clock output 1 (unprogrammed) 1 wdton watchdog timer always on 1 (unprogrammed) 0 rstdisbl external reset disable 1 (unprogrammed) 109 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 15.3.4 signature section the signature section is a dedicated memory area used for storing miscellaneous device information, such as the device signature. most of this memory section is reserved for internal use, as shown in table 15-7 . attiny4/5/9/10 have a three-byte sig nature code, which can be used to ident ify the device. the three bytes reside in the signature section, as shown in table 15-7 . the signature data for at tiny4/5/9/10 is given in table 15-8 . 15.3.5 calibration section attiny4/5/9/10 have one calibration byte . the calibration byte contains the calib ration data for the internal oscillator and resides in the calibration section, as shown in table 15-9 . during reset, the calibration byte is automatically written into the osccal register to ensure correct frequency of the calibrated internal oscillator. 15.3.5.1 latching of calibration value to ensure correct frequency of the calibrated internal oscillato r the calibration value is au tomatically writ ten into the osccal register during reset. 15.4 accessing the nvm nvm lock bits, and all flash memory sections are mapped to the data space as shown in figure 5-1 on page 15 . the nvm can be accessed for read and programming via the locations mapped in the data space. the nvm controller recognises a set of commands that can be used to instruct the controller what type of pro- gramming task to perform on the nvm. commands to the nvm controller are issued via the nvm command register. see ?nvmcmd - non-volatile memory command register? on page 114 . after the selected command has been loaded, the operation is st arted by writing data to the nvm locations mapped to the data space. table 15-7. signature bytes signature word address signature word data high byte low byte 0x00 device id 1 manufacturer id 0x01 reserved for internal use device id 2 0x02 ... 0x0f reserved for internal use reserved for internal use table 15-8. signature codes part signature bytes manufacturer id device id 1 device id 2 attiny4 0x1e 0x8f 0x0a attiny5 0x1e 0x8f 0x09 attiny9 0x1e 0x90 0x08 attiny10 0x1e 0x90 0x03 table 15-9. calibration byte calibration word address calibration word data high byte low byte 0x00 reserved internal oscillator calibration value 0x01 ... 0x07 reserved reserved 110 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 when the nvm controller is busy perform ing an operation it will signal this vi a the nvm busy flag in the nvm con- trol and status register. see ?nvmcsr - non-volatile memory control and status register? on page 114 . the nvm command register is blocked for write access as long as the busy flag is active. this is to ensure that the current command is fully executed before a new command can start. programming any part of the nvm will automa tically inhibit the following operations: ? all programming to any other part of the nvm ? all reading from any nvm location attiny4/5/9/10 support only external programming. internal programming ope rations to nvm have been disabled, which means any internal attempt to write or erase nvm locations will fail. 15.4.1 addressing the flash the data space uses byte accessing but since the flash sections are accessed as wo rds and organized in pages, the byte-address of the data space must be converted to the word-address of the flash section. this is illustrated in figure 15-1 . also, see table 15-3 on page 107 . the most significant bits of the data space address sele ct the nvm lock bits or the flash section mapped to the data memory. the word address within a page (waddr) is held by bits [waddrmsb:1], and the page address (paddr) by bits [paddrmsb:waddrmsb+ 1]. together, paddr and waddr fo rm the absolute address of a word in the flash section. the least significant bit of the flash section address is used to select the low or high byte of the word. figure 15-1. addressing the flash memory 15.4.2 reading the flash the flash can be read from the data memory mapped locati ons one byte at a time. fo r read operations, the least significant bit (bit 0) is used to select th e low or high byte in the word address. if this bit is zero, the low byte is read, and if it is one, the high byte is read. 00 pag e 01 02 sectionend word 00 01 pageend flash section flash pag e 0/1 waddr paddr 1 waddrmsb paddrmsb 16 address pointer ... ... ... ... ... ... page address within a flash section word address within a flash pag e low/high byte select waddrmsb+1 111 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 15.4.3 programming the flash the flash can be written word-by-word. before writing a fl ash word, the flash target location must be erased. writing to an un-erased flash word will corrupt its content. the flash is word-accessed for writing, and the data space uses byte-addressing to access flash that has been mapped to data memory. it is therefore important to write the word in the correct order to the flash, namely low bytes before high bytes. first, the lo w byte is written to the temporary buf fer. then, writing the high byte latches both the high byte and the low byte into the flash word buffer, star ting the write operation to flash. the flash erase operations can only pe rformed for the entire flash sections. the flash programming sequence is as follows: 1. perform a flash section erase or perform a chip erase 2. write the flash section word by word 15.4.3.1 chip erase the chip erase command will erase the entire code se ction of the flash memory and the nvm lock bits. for security reasons, the nvm lock bits are not reset before the code section has been completely erased. configura- tion, signature and calibrati on sections are not changed. before starting the chip erase, the nvmcmd register must be loaded with the chip_erase command. to start the erase operation a dummy byte must be written into the high byte of a word location that resides inside the flash code section. the nvmbsy bit remains set until erasing has been completed. while the fl ash is being erased nei- ther flash buffer loading nor flash reading can be performed. the chip erase can be carried out as follows: 1. write the chip_erase command to the nvmcmd register 2. start the erase operation by writing a dummy byte to the high byte of any word location inside the code section 3. wait until the nvmbsy bit has been cleared 15.4.3.2 erasing the code section the algorithm for erasing all pages of the flash code section is as follows: 1. write the section_erase command to the nvmcmd register 2. start the erase operation by writing a dummy byte to the high byte of any word location inside the code section 3. wait until the nvmbsy bit has been cleared 15.4.3.3 writing a code word the algorithm for writing a word to the code section is as follows: 1. write the word_write command to the nvmcmd register 2. write the low byte of the data into the low byte of a word location 3. write the high byte of the data into the high byte of the same word lo cation. this will start the flash write operation 4. wait until the nvmbsy bit has been cleared 112 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 15.4.3.4 erasing the configuration section the algorithm for erasing the conf iguration section is as follows: 1. write the section_erase command to the nvmcmd register 2. start the erase operation by writing a dummy byte to the high byte of any word location inside the configu- ration section 3. wait until the nvmbsy bit has been cleared 15.4.3.5 writing a configuration word the algorithm for writing a conf iguration word is as follows. 1. write the word_write command to the nvmcmd register 2. write the low byte of the data to the low byte of a configuration word location 3. write the high byte of the data to the high byte of the same configurat ion word location. this will start the flash write operation. 4. wait until the nvmbsy bit has been cleared 15.4.4 reading nvm lock bits the non-volatile memory lock byte can be read from the mapped location in data memory. 15.4.5 writing nvm lock bits the algorithm for writing the lock bits is as follows. 1. write the word_write command to the nvmcmd register. 2. write the lock bits value to the non-volatile memory lock byte location. this is the low byte of the non- volatile memory lock word. 3. start the nvm lock bit write operation by writing a dummy byte to the high byte of the nvm lock word location. 4. wait until the nvmbsy bit has been cleared. 15.5 self programming the attiny4/5/9/10 don't s upport internal programming. 15.6 external programming the method for programming the non-volatile memories by means of an external programmer is referred to as external programming. external programming can be done both in-system or in mass production. the non-volatile memories can be externally programmed via the tiny programming interface (tpi). for details on the tpi, see ?programming interface? on page 95 . using the tpi, the external programmer can access the nvm control and status registers mappe d to i/o space and the nvm memory mapped to data memory space. 15.6.1 entering external programming mode the tpi must be enabled before external programming mode can be entered. the following procedure describes, how to enter the external programming mode after the tpi has been enabled: 1. make a request for enabling nv m programming by sending the nv m memory access key with the skey instruction. 2. poll the status of the nvmen bit in tpisr until it has been set. 113 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 refer to the tiny programming interface description on page 95 for more detailed information of enabling the tpi and programming the nvm. 15.6.2 exiting extern al programming mode clear the nvm enable bit to disable nvm programming, then release the reset pin. see nvmen bit in ?tpisr ? tiny programming interface status register? on page 105 . 114 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 15.7 register description 15.7.1 nvmcsr - non-volatile memo ry control and status register ? bit 7 - nvmbsy: non-volatile memory busy this bit indicates the nvm memory (flash memory and lo ck bits) is busy, being programmed. this bit is set when a program operation is started, and it remain s set until the operation has been completed. ? bit 6:0 - res: reserved bits these bits are reserved and will always be read as zero. 15.7.2 nvmcmd - non-volatile memory command register ? bit 7:6 - res: reserved bits these bits are reserved and will always read zero. ? bit 5:0 - nvmcmd[5:0]: non-volatile memory command these bits define the programming commands for the flash, as shown in table 15-10 . bit 7 6543210 0x32 nvmbsy ? ? ? ? ? ? ?nvmcsr read/writer/wrrrrrrr initial value0 0000000 bit 76543210 0x33 ? ? nvmcmd[5:0] nvmcmd read/write r r r/w r/w r/w r/w r/w r/w initial value00000000 table 15-10. nvm programming commands operation type nvmcmd mnemonic description binary hex general 0b000000 0x00 no_operation no operation 0b010000 0x10 chip_erase chip erase section 0b010100 0x14 section_erase section erase word 0b011101 0x1d word_write word write 115 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 16. electrical characteristics 16.1 absolute maximum ratings* 16.2 dc characteristics operating temperature.................................. -55 ? c to +125 ? c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c voltage on any pin except reset with respect to ground ................................-0.5v to v cc +0.5v voltage on reset with respect to ground......-0.5v to +13.0v maximum operating voltage ............................................ 6.0v dc current per i/o pin ............................................... 40.0 ma dc current v cc and gnd pins................................ 200.0 ma table 16-1. dc characteristics. t a = -40 ? c to +85 ? c symbol parameter condition min. typ. max. units v il input low voltage v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v -0.5 0.2v cc 0.3v cc v v ih input high-voltage except reset pin v cc = 1.8v - 2.4v v cc = 2.4v - 5.5v 0.7v cc (1) 0.6v cc (1) v cc +0.5 (2) v input high-voltage reset pin v cc = 1.8v to 5.5v 0.9v cc (1) v cc +0.5 (2) v v ol output low voltage (3) except reset pin (5) i ol = 10 ma, v cc = 5v i ol = 5 ma, v cc = 3v 0.6 0.5 v v oh output high-voltage (4) except reset pin (5) i oh = -10 ma, v cc = 5v i oh = -5 ma, v cc = 3v 4.3 2.5 v i lil input leakage current i/o pin vcc = 5.5 v, pin low (absolute value) <0.05 1 a i lih input leakage current i/o pin vcc = 5.5 v, pin high (absolute value) <0.05 1 a r rst reset pull-up resistor vcc = 5.5 v, input low 30 60 k ? r pu i/o pin pull-up resistor vcc = 5.5 v, input low 20 50 k ? i aclk analog comparator input leakage current v cc = 5v v in = v cc /2 -50 50 na 116 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 notes: 1. ?min? means the lowest value wher e the pin is guaranteed to be read as high. 2. ?max? means the highest value where the pin is guaranteed to be read as low. 3. although each i/o port can sink more than the test conditions (10 ma at v cc = 5v, 5 ma at v cc = 3v) under steady state conditions (non-transient ), the sum of all i ol (for all ports) should not exceed 60 ma. if i ol exceeds the test conditions, v ol may exceed the related specification. pi ns are not guaranteed to sink current greater than the list ed test condition. 4. although each i/o port can source more than the test conditions (10 ma at v cc = 5v, 5 ma at v cc = 3v) under steady state conditions (non-transient ), the sum of all i oh (for all ports) should not exceed 60 ma. if i oh exceeds the test condition, v oh may exceed the related specification. pins are not guaranteed to source current gr eater than the listed test condition. 5. the reset pin must tolerate high voltages when entering and op erating in programming modes and, as a consequence, has a weak drive strength as compared to regular i/o pins. see figure 17-25 on page 134 , and figure 17-26 on page 134 . 6. values are with external clo ck using methods described in ?minimizing power consumption? on page 24 . power reduction is enabled (prr = 0xff) and there is no i/o drive. 7. bod disabled. 16.3 speed the maximum operating frequency of the device depends on v cc . the relationship between supply voltage and maximum operating frequency is piecewise linear, as shown in figure 16-1 . figure 16-1. maximum frequency vs. v cc i cc power supply current (6) active 1mhz, v cc = 2v 0.2 0.5 ma active 4mhz, v cc = 3v 0.8 1.2 ma active 8mhz, v cc = 5v 2.7 4 ma idle 1mhz, v cc = 2v 0.02 0.2 ma idle 4mhz, v cc = 3v 0.13 0.5 ma idle 8mhz, v cc = 5v 0.6 1.5 ma power-down mode (7) wdt enabled, v cc = 3v 4.5 10 a wdt disabled, v cc = 3v 0.15 2 a table 16-1. dc characteristics. t a = -40 ? c to +85 ? c (continued) symbol parameter condition min. typ. max. units 4 mhz 8 mhz 1.8v 5.5v 4.5v 2.7v 12 mhz 117 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 16.4 clock characteristics 16.4.1 accuracy of calibra ted internal oscillator it is possible to manually calibrate the internal oscillato r to be more accurate than de fault factory ca libration. note that the oscillator frequency depends on temperature and voltage. voltage and temperat ure characteristics can be found in figure 17-39 on page 141 and figure 17-40 on page 141 . notes: 1. accuracy of oscillator frequency at calibrat ion point (fixed temperature and fixed voltage). 16.4.2 external clock drive figure 16-2. external clock drive waveform table 16-2. calibration accuracy of internal rc oscillator calibration method target frequency v cc temperature accuracy at given voltage & temperature (1) factory calibration 8.0 mhz 3v 25 ? c10% user calibration fixed frequency within: 7.3 ? 8.1 mhz fixed voltage within: 1.8v ? 5.5v fixed temp. within: -40 ? c ? 85 ? c 1% v il1 v ih1 table 16-3. external clock driv e characteristics symbol parameter v cc = 1.8 - 5.5v v cc = 2.7 - 5.5v v cc = 4.5 - 5.5v units min. max. min. max. min. max. 1/t clcl clock frequency 0 4 0 8 0 12 mhz t clcl clock period 250 125 83 ns t chcx high time 100 50 33 ns t clcx low time 100 50 33 ns t clch rise time 2.0 1 0.6 ? s t chcl fall time 2.0 1 0.6 ? s ? t clcl change in period fr om one clock cycle to the next 2 2 2 % 118 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 16.5 system and reset characteristics note: 1. values are guidelines, only 16.5.1 power-on reset note: 1. values are guidelines, only 2. threshold where device is released from reset when voltage is rising 3. the power-on reset will not work unless the supply voltage has been below v poa 16.5.2 v cc level monitor note: 1. typical values at room temperature table 16-4. reset, vlm, and internal voltage characteristics symbol parameter condition min (1) typ (1) max (1) units v rst reset pin threshold voltage 0.2 v cc 0.9v cc v t rst minimum pulse width on reset pin v cc = 1.8v v cc = 3v v cc = 5v 2000 700 400 ns t tout time-out after reset 32 64 128 ms table 16-5. characteristics of enhanced power-on reset. t a = -40 - 85 ? c symbol parameter min (1) typ (1) max (1) units v por release threshold of power-on reset (2) 1.1 1.4 1.6 v v poa activation threshold of power-on reset (3) 0.6 1.3 1.6 v sr on power-on slope rate 0.01 v/ms table 16-6. voltage level monitor thresholds parameter min typ (1) max units trigger level vlm1l 1.1 1.4 1.6 v trigger level vlm1h 1.4 1.6 1.8 trigger level vlm2 2.0 2.5 2.7 trigger level vlm3 3.2 3.7 4.5 settling time vmlm2,vlm3 (vlm1h,vlm1l) 5 (50) s 119 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 16.6 analog comparat or characteristics 16.7 adc characteristics (attiny5/10, only) table 16-7. analog comparator characteristics, t a = -40 ? c - 85 ? c symbol parameter condition min typ max units v aio input offset voltage v cc = 5v, v in = v cc / 2 < 10 40 mv i lac input leakage current v cc = 5v, v in = v cc / 2 -50 50 na t apd analog propagation delay (from saturation to slight overdrive) v cc = 2.7v 750 ns v cc = 4.0v 500 analog propagation delay (large step change) v cc = 2.7v 100 v cc = 4.0v 75 t dpd digital propagation delay v cc = 1.8v - 5.5 1 2 clk table 16-8. adc characteristics. t = -40 ? c ? 85 ? c. v cc = 2.5v ? 5.5v symbol parameter condition min typ max units resolution 8bits absolute accuracy (including inl, dnl, and quantization, gain and offset errors) v ref = v cc = 4v, adc clock = 200 khz 1.0 lsb v ref = v cc = 4v, adc clock = 200 khz noise reduction mode 1.0 lsb integral non-linearity (inl) (accuracy after offset and gain calibration) v ref = v cc = 4v, adc clock = 200 khz 1.0 lsb differential non-linearity (dnl) v ref = v cc = 4v, adc clock = 200 khz 0.5 lsb gain error v ref = v cc = 4v, adc clock = 200 khz 1.0 lsb offset error v ref = v cc = 4v, adc clock = 200 khz 1.0 lsb conversion time free running conversion 65 260 s clock frequency 50 200 khz v in input voltage gnd v ref v input bandwidth 7.7 khz r ain analog input resistance 100 m ? adc conversion output 0 255 lsb 120 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 16.8 serial programming characteristics figure 16-3. serial programming timing table 16-9. serial programming characteristics, t a = -40 ? c to 85 ? c, v cc = 5v 5% (unless otherwise noted) symbol parameter min typ max units 1/t clcl clock frequency 2 mhz t clcl clock period 500 ns t clch clock low pulse width 200 ns t chch clock high pulse width 200 ns t ivch data input to clock high setup time 50 ns t chix data input hold time after clock high 100 ns t clov data output valid after clock low time 200 ns t chix tpidata t ivch t chcl t clch t clcl tpiclk t clov transmit mode receive mode 121 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 17. typical characteristics the data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. thus , the data should be treated as in dications of how t he part will behave. the following charts show typical behavior. these figu res are not tested during manuf acturing. during characteri- sation devices are operated at frequencies higher than test limits but they are not guaran teed to function properly at frequencies higher than the ordering code indicates. all current consumption measurements are performed with a ll i/o pins configured as inputs and with internal pull- ups enabled. current consumption is a function of several factors such as operating voltage, operating frequency, loading of i/o pins, switching rate of i/o pins, code ex ecuted and ambient temperature. the dominating factors are operating voltage and frequency. a sine wave generator with rail-to-rail output is used as clock source but current consumption in power-down mode is independent of clock selection. the difference between current consumption in power-down mode with watchdog timer enabled and power-down mode with watchdog timer disabled represents the differential current drawn by the watchdog timer. the current drawn from pins with a capacitive lo ad may be estimated (for one pin) as follows: where v cc = operating voltage, c l = load capacitance and f sw = average switching frequency of i/o pin. 17.1 supply current of i/o modules tables and formulas below can be used to calculate addi tional current consumption for the different i/o modules in active and idle mode. enabling and disabling of i/o module s is controlled by the power reduction register. see ?power reduction register? on page 24 for details. note: 1. the adc is available in attiny5/10, only table 17-2 below can be used for calculating typical current c onsumption for other supply voltages and frequencies than those mentioned in the table 17-1 above. note: 1. the adc is available in attiny5/10, only i cp v cc c l f ? ? sw ? table 17-1. additional current consumption for the different i/o modules (absolute values) prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz prtim0 6.6 ua 40.0 ua 153.0 ua pradc (1) 29.6 ua 88.3 ua 333.3 ua table 17-2. additional current consumption (percentage) in active and idle mode prr bit current consumption additional to active mode with external clock (see figure 17-1 and figure 17-2 ) current consumption additional to idle mode with external clock (see figure 17-7 and figure 17-8 ) prtim0 2.3 % 10.4 % pradc (1) 6.7 % 28.8 % 122 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 17.2 active supply current figure 17-1. active supply current vs. low frequency (0.1 - 1.0 mhz) figure 17-2. active supply current vs. frequency (1 - 12 mhz) active supply current vs. low frequency (prr=0xff) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 fre q uency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v active supply current vs. frequency (prr=0xff) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 024681012 fre q uency (mhz) i cc (ma) 123 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 17-3. active supply current vs. v cc (internal osc illator, 8 mhz) figure 17-4. active supply current vs. v cc (internal osc illator, 1 mhz) active supply current vs. v cc internal oscillator, 8 mhz 85 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 3.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) active supply current vs. v cc internal oscillator, 1 mhz 85 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 124 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 17-5. active supply current vs. v cc (internal osc illator, 128 khz) figure 17-6. active supply current vs. v cc (external clock, 32 khz) active supply current vs. v cc internal oscillator, 128 khz 85 c 25 c -40 c 0 0.02 0.04 0.06 0.08 0.1 0.12 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) active supply current vs. v cc internal oscillator, 32 khz 85 c 25 c -40 c 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 125 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 17.3 idle supply current figure 17-7. idle supply current vs. low frequency (0.1 - 1.0 mhz) figure 17-8. idle supply current vs. frequency (1 - 12 mhz) idle supply current vs. low frequency (prr=0xff) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0,01 0,02 0,03 0,04 0,05 0,06 0,07 0,08 0,09 0,1 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 frequency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v idle supply current vs. frequency (prr=0xff) 0 0,2 0,4 0,6 0,8 1 2 1 0 1 8 6 4 2 0 frequency (mhz) i cc (ma) 126 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 17-9. idle supply current vs. v cc (internal osc illator, 8 mhz) figure 17-10. idle supply current vs. v cc (internal osc illator, 1 mhz) idle supply current vs. v cc internal rc oscillator, 8 mhz 85 c 25 c -40 c 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (ma) idle supply current vs. v cc internal rc oscillator, 1 mhz 85 c 25 c -40 c 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (ma) 127 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 17.4 power-down supply current figure 17-11. power-down supply current vs. v cc (watchdog timer disabled) figure 17-12. power-down supply current vs. v cc (watchdog timer enabled) power-down supply current vs. v cc watchdog timer disabled 85 c 25 c -40 c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) power-down supply current vs. v cc watchdog timer enabled 85 c 25 c -40 c 0 1 2 3 4 5 6 7 8 9 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (ua) 128 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 17.5 pin pull-up figure 17-13. i/o pin pull-up resistor current vs. input voltage (v cc = 1.8v) figure 17-14. i/o pin pull-up resistor current vs. input voltage (v cc = 2.7v) i/o pin pull-up resistor current vs. input voltage 85 c 25 c -40 c 0 10 20 30 40 50 60 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 v op (v) i op (ua) i/o pin pull-up resistor current vs. input voltage 85 c 25 c -40 c 0 10 20 30 40 50 60 70 80 3 5 , 2 2 5 , 1 1 5 , 0 0 v op (v) i op (ua) 129 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 17-15. i/o pin pull-up resistor current vs. input voltage (v cc = 5v) figure 17-16. reset pull-up resistor curr ent vs. reset pin voltage (v cc = 1.8v) i/o pin pull-up resistor current vs. input voltage 85 c 25 c -40 c 0 20 40 60 80 100 120 140 160 6 5 4 3 2 1 0 v op (v) i op (ua) reset pull-up resistor current vs. reset pin voltage 85 c 25 c -40 c 0 5 10 15 20 25 30 35 40 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 v reset (v) i reset (ua) 130 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 17-17. reset pull-up resistor curr ent vs. reset pin voltage (v cc = 2.7v) figure 17-18. reset pull-up resistor curr ent vs. reset pin voltage (v cc = 5v) reset pull-up resistor current vs. reset pin voltage 85 c 25 c -40 c 0 10 20 30 40 50 60 3 5 , 2 2 5 , 1 1 5 , 0 0 v reset (v) i reset (ua) reset pull-up resistor current vs. reset pin voltage 85 c 25 c -40 c 0 20 40 60 80 100 120 00,511,522,533,544,55 v reset (v) i reset (ua) 131 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 17.6 pin driver strength figure 17-19. i/o pin output voltage vs. sink current (v cc = 1.8v) figure 17-20. i/o pin output voltage vs. sink current (v cc = 3v) i/o pin output voltage vs. sink current v cc = 1.8v 85 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 i ol (ma) v ol (v) i/o pin output voltage vs. sink current v cc = 3v 85 c 25 c -40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 012345678910 i ol (ma) v ol (v) 132 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 17-21. i/o pin output voltage vs. sink current (v cc = 5v) figure 17-22. i/o pin output voltage vs. source current (v cc = 1.8v) i/o pin output voltage vs. sink current v cc = 5v 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 0 2 4 6 8 10 12 14 16 18 20 i ol (ma) v ol (v) i/o pin output voltage vs. source current v cc = 1.8v 85 c 25 c -40 c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 i oh (ma) v oh (v) 133 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 17-23. i/o pin output voltage vs. source current (v cc = 3v) figure 17-24. i/o pin output voltage vs. source current (v cc = 5v) i/o pin output voltage vs. source current v cc = 3v 85 c 25 c -40 c 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 012345678910 i oh (ma) v oh (v) i/o pin output voltage vs. source current v cc = 5v 85 c 25 c -40 c 4 4.2 4.4 4.6 4.8 5 5.2 02468101214161820 i oh (ma) v oh (v) 134 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 17-25. reset pin as i/o, output voltage vs. sink current figure 17-26. reset pin as i/o, output voltage vs. source current output voltage vs. sink current reset pin as i/o 5.0 v 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 4 3 2 1 0 i ol (ma) v ol (v) 3.0 v 1.8 v output voltage vs. source current reset pin as i/o 5.0 v 3.0 v 0 1 2 3 4 5 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 i oh (ma) v oh (v) 1.8 v 135 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 17.7 pin threshold and hysteresis figure 17-27. i/o pin input threshold voltage vs. v cc (v ih , io pin read as ?1?) figure 17-28. i/o pin input threshold voltage vs. v cc (v il , io pin read as ?0?) i/o pin input threshold voltage vs. v cc vih, io pin read as '1' 85 c 25 c -40 c 0 0,5 1 1,5 2 2,5 3 3,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) threshold (v) i/o pin input threshold voltage vs. v cc vil, io pin read as '0' 85 c 25 c -40 c 0 0,5 1 1,5 2 2,5 3 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) threshold (v) 136 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 17-29. i/o pin input hysteresis vs. v cc figure 17-30. reset pin as i/o, input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) i/o pin input hysteresis vs. v cc 85 c 25 c -40 c 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) input hysteresis (v) reset pin as i/o threshold voltage vs. v cc vih, reset read as '1' 85 c 25 c -40 c 0 0,5 1 1,5 2 2,5 3 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) threshold (v) 137 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 17-31. reset pin as i/o, input threshold voltage vs. v cc (v il , i/o pin read as ?0?) figure 17-32. reset input hysteresis vs. v cc (reset pin used as i/o) reset pin as i/o threshold voltage vs. v cc vil, reset read as '0' 85 c 25 c -40 c 0 0,5 1 1,5 2 2,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) threshold (v) reset pin as i/o, input hysteresis vs. vcc v il , pin read as "0" 85 c 25 c -40 c 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) input hysteresis (v) 138 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 17-33. reset input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) figure 17-34. reset input threshold voltage vs. v cc (v il , i/o pin read as ?0?) reset input threshold voltage vs. v cc vih, io pin read as '1' 85 c 25 c -40 c 0 0,5 1 1,5 2 2,5 1,522,533,544,555,5 v cc (v) threshold (v) reset input threshold voltage vs. v cc vil, io pin read as '0' 85 c 25 c -40 c 0 0,5 1 1,5 2 2,5 1,522,533,544,555,5 v cc (v) threshold (v) 139 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 17-35. reset pin, input hysteresis vs. v cc 17.8 analog comparator offset figure 17-36. analog comparator offset reset pin input hysteresis vs. v cc 85 c 25 c -40 c 0 0,2 0,4 0,6 0,8 1 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) input hysteresis (v) analog comparator offset v cc = 5v 85 25 -40 0 0.002 0.004 0.006 5 4 3 2 1 0 v in offset 140 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 17.9 internal oscillator speed figure 17-37. watchdog oscillator frequency vs. v cc figure 17-38. watchdog oscillator freq uency vs. temperature watchdog oscillator frequency vs. operating voltage 85 c 25 c -40 c 99 100 101 102 103 104 105 106 107 108 109 110 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) fre q uency (khz) watchdog oscillator frequency vs. temperature 5.5 v 4.0 v 3.3 v 2.7 v 1.8 v 100 101 102 103 104 105 106 107 108 109 110 -60 -40 -20 0 20 40 60 80 100 temperature fre q uency (khz) 141 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 17-39. calibrated oscillato r frequency vs. v cc figure 17-40. calibrated oscillator freq uency vs. temperature calibrated 8.0mhz oscillator frequency vs. operating voltage 85 c 25 c -40 c 7.4 7.6 7.8 8 8.2 8.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) fre q uency (mhz) calibrated 8.0mhz oscillator frequency vs. temperature 5.0 v 3.0 v 1.8 v 7.6 7.7 7.8 7.9 8 8.1 8.2 8.3 -40 -20 0 20 40 60 80 100 temperature fre q uency (mhz) 142 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 17-41. calibrated oscillator freq uency vs, osccal value 17.10 vlm thresholds figure 17-42. vlm1l threshold of v cc level monitor calibrated 8.0mhz rc oscillator frequency vs. osccal value v cc = 3v 85 c 25 c -40 c 0 2 4 6 8 10 12 14 16 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 osccal (x1) fre q uency (mhz) vlm threshold vs. temperature vlm2:0 = 001 1.34 1.35 1.36 1.37 1.38 1.39 1.4 1.41 1.42 -40 -20 0 20 40 60 80 100 temperature (c) threshold (v) 143 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 17-43. vlm1h threshold of v cc level monitor figure 17-44. vlm2 threshold of v cc level monitor vlm threshold vs. temperature vlm2:0 = 010 1.4 1.45 1.5 1.55 1.6 1.65 1.7 -40 -20 0 20 40 60 80 100 temperature (c) threshold (v) vlm threshold vs. temperature vlm2:0 = 011 2.43 2.44 2.45 2.46 2.47 2.48 -40 -20 0 20 40 60 80 100 temperature (c) threshold (v) 144 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 17-45. vlm3 threshold of v cc level monitorr2 17.11 current consumpti on of peripheral units figure 17-46. adc current vs. v cc (attiny5/10, only) vlm threshold vs. temperature vlm2:0 = 100 3.4 3.5 3.6 3.7 3.8 3.9 -40 -20 0 20 40 60 80 100 temperature (c) threshold (v) adc current vs. v cc 4.0 mhz frequency 0 100 200 300 400 500 600 700 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 145 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 17-47. analog comparator current vs. v cc figure 17-48. v cc level monitor current vs. v cc analog comparator current vs. v cc 0 20 40 60 80 100 120 140 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (ua) 25 ?c vlm supply current vs. v cc vlm2:0 = 100 vlm2:0 = 011 vlm2:0 = 010 vlm2:0 = 001 vlm2:0 = 000 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 146 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 figure 17-49. temperature dependence of vlm current vs. v cc figure 17-50. watchdog timer current vs. v cc vlm supply current vs. v cc vlm2:0 = 001 85 c 25 c -40 c 0 50 100 150 200 250 300 350 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 85 c 25 c -40 c 0 1 2 3 4 5 6 7 8 9 1,5 2 2,5 3 3,5 4 4,5 5 5,5 v cc (v) i cc (ua) watchdog timer current vs. v cc 147 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 17.12 current consumption in reset and reset pulsewidth figure 17-51. reset supply current vs. v cc (0.1 - 1.0 mhz, excluding current through the reset pull-up) note: the default clock source fo r the device is always the internal 8 mhz o scillator. hence, current consumption in reset remains unaffected by external clock signals. figure 17-52. minimum reset pulse width vs. v cc reset supply current vs. v cc excluding current through the reset pullup 5.5 v 5.0 v 4.5 v 4.0 v 3.3 v 2.7 v 1.8 v 0 0,1 0,2 0,3 0,4 0,5 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 frequency (mhz) i cc (ma) minimum reset pulse width vs. v cc 85 c 25 c -40 c 0 500 1000 1500 2000 2500 1,522,533,544,555,5 v cc (v) pulsewidth (ns) 148 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 18. register summary note: 1. for compatibility with future devices, reserved bits shou ld be written to zero if accesse d. reserved i/o memory addresse s address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 0x3f sreg i t h s v n z c page 12 0x3e sph stack pointer high byte page 12 0x3d spl stack pointer low byte page 12 0x3c ccp cpu change protection byte page 11 0x3b rstflr ? ? ? ?wdrf ? extrf porf page 34 0x3a smcr ? ? ? ? sm2 sm1 sm0 se page 25 0x39 osccal oscillator calibration byte page 21 0x38 reserved ? ? ? ? ? ? ? ? 0x37 clkmsr ? ? ? ? ? ? clkms1 clkms0 page 21 0x36 clkpsr ? ? ? ? clkps3 clkps2 clkps1 clkps0 page 22 0x35 prr ? ? ? ? ? ? pradc prtim0 page 26 0x34 vlmcsr vlmf vlmie ? ? ? vlm2 vlm1 vlm0 page 33 0x33 nvmcmd ? ? nvm comman page 114 0x32 nvmcsr nvmbsy ? ? ? ? ? ? ? page 114 0x31 wdtcsr wdif wdie wdp3 ? wde wdp2 wdp1 wdp0 page 32 0x30 reserved ? ? ? ? ? ? ? ? 0x2f gtccr tsm ? ? ? ? ? ?psr page 78 0x2e tccr0a com0a1 com0a0 com0b1 com0b0 ? ? wgm01 wgm00 page 72 0x2d tccr0b icnc0 ices0 ? wgm03 wgm02 cs02 cs01 cs00 page 74 0x2c tccr0c foc0a foc0b ? ? ? ? ? ? page 75 0x2b timsk0 ? ?icie0 ? ? ocie0b ocie0a toie0 page 77 0x2a tifr0 ? ?icf0 ? ? ocf0b ocf0a tov0 page 78 0x29 tcnt0h timer/counter0 ? counter register high byte page 76 0x28 tcnt0l timer/counter0 ? counter register low byte page 76 0x27 ocr0ah timer/counter0 ? compare register a high byte page 76 0x26 ocr0al timer/counter0 ? compare register a low byte page 76 0x25 ocr0bh timer/counter0 ? compare register b high byte page 76 0x24 ocr0bl timer/counter0 ? compare register b low byte page 76 0x23 icr0h timer/counter0 - input capture register high byte page 77 0x22 icr0l timer/counter0 - input capture register low byte page 77 0x21 reserved ? ? ? ? ? ? ? ? 0x20 reserved ? ? ? ? ? ? ? ? 0x1f acsr acd ? aco aci acie acic acis1 acis0 page 80 0x1e reserved ? ? ? ? ? ? ? ? 0x1d adcsra aden adsc adate adif adie adps2 adps1 adps0 page 92 0x1c adcsrb ? ? ? ? ? adts2 adts1 adts0 page 93 0x1b admux ? ? ? ? ? ? mux1 mux0 page 92 0x1a reserved ? ? ? ? ? ? ? ? 0x19 adcl adc conversion result page 94 0x18 reserved ? ? ? ? ? ? ? ? 0x17 didr0 ? ? ? ? adc3d adc2d adc1d adc0d page 81, page 94 0x16 reserved ? ? ? ? ? ? ? ? 0x15 eicra ? ? ? ? ? ? isc01 isc00 page 37 0x14 eifr ? ? ? ? ? ? ? intf0 page 38 0x13 eimsk ? ? ? ? ? ? ? int0 page 38 0x12 pcicr ? ? ? ? ? ? ? pcie0 page 39 0x11 pcifr ? ? ? ? ? ? ?pcif0 page 39 0x10 pcmsk ? ? ? ? pcint3 pcint2 pcint1 pcint0 page 39 0x0f reserved ? ? ? ? ? ? ? ? 0x0e reserved ? ? ? ? ? ? ? ? 0x0d reserved ? ? ? ? ? ? ? ? 0x0c portcr ? ? ? ? ? ? bbmb ? page 50 0x0b reserved ? ? ? ? ? ? ? ? 0x0a reserved ? ? ? ? ? ? ? ? 0x09 reserved ? ? ? ? ? ? ? ? 0x08 reserved ? ? ? ? ? ? ? ? 0x07 reserved ? ? ? ? ? ? ? ? 0x06 reserved ? ? ? ? ? ? ? ? 0x05 reserved ? ? ? ? ? ? ? ? 0x04 reserved ? ? ? ? ? ? ? ? 0x03 pueb ? ? ? ? pueb3 pueb2 pueb1 pueb0 page 50 0x02 portb ? ? ? ? portb3 portb2 portb1 portb0 page 51 0x01 ddrb ? ? ? ? ddrb3 ddrb2 ddrb1 ddrb0 page 51 0x00 pinb ? ? ? ? pinb3 pinb2 pinb1 pinb0 page 51 149 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 should never be written. 2. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical one to them. note that, unlike most other avrs, the cbi and sbi instructions will only operation the specif ied bit, and can therefore be used on r egisters containing such status flags. the cbi and sbi instructions work wit h registers 0x00 to 0x1f only. 4. the adc is available in attiny5/10, only. 150 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 19. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add without carry rd ? rd + rr z,c,n,v,s,h 1 adc rd, rr add with carry rd ? rd + rr + c z,c,n,v,s,h 1 sub rd, rr subtract without carry rd ? rd - rr z,c,n,v,s,h 1 subi rd, k subtract immediate rd ? rd - k z,c,n,v,s,h 1 sbc rd, rr subtract with carry rd ? rd - rr - c z,c,n,v,s,h 1 sbci rd, k subtract immediate with carry rd ? rd - k - c z,c,n,v,s,h 1 and rd, rr logical and rd ?? rd ? rr z,n,v,s 1 andi rd, k logical and with immediate rd ? rd ?? k z,n,v,s 1 or rd, rr logical or rd ? rd v rr z,n,v,s 1 ori rd, k logical or with immediate rd ?? rd v k z,n,v,s 1 eor rd, rr exclusive or rd ? rd ? rr z,n,v,s 1 com rd one?s complement rd ? $ff ? rd z,c,n,v,s 1 neg rd two?s complement rd ? $00 ? rd z,c,n,v,s,h 1 sbr rd,k set bit(s) in register rd ? rd v k z,n,v,s 1 cbr rd,k clear bit(s) in register rd ? rd ? ($ffh - k) z,n,v,s 1 inc rd increment rd ? rd + 1 z,n,v,s 1 dec rd decrement rd ? rd ? 1 z,n,v,s 1 tst rd test for zero or minus rd ? rd ? rd z,n,v,s 1 clr rd clear register rd ? rd ? rd z,n,v,s 1 ser rd set register rd ? $ff none 1 branch instructions rjmp k relative jump pc ?? pc + k + 1 none 2 ijmp indirect jump to (z) pc(15:0) ? z, pc(21:16) ? 0none2 rcall k relative subroutine call pc ? pc + k + 1 none 3/4 icall indirect call to (z) pc(15:0) ? z, pc(21:16) ? 0none3/4 ret subroutine return pc ? stack none 4/5 reti interrupt return pc ? stack i 4/5 cpse rd,rr compare, skip if equal if (rd = rr) pc ?? pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, c,n,v,s,h 1 cpc rd,rr compare with carry rd ? rr ? c z, c,n,v,s,h 1 cpi rd,k compare with immediate rd ? k z, c,n,v,s,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc ? pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc ? pc + 2 or 3 none 1/2/3 sbic a, b skip if bit in i/o register cleared if (i/o(a,b)=0) pc ? pc + 2 or 3 none 1/2/3 sbis a, b skip if bit in i/o register is set if (i/o(a,b)=1) pc ? pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc ? pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc ? pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc ? pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc ? pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc ? pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc ? pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc ? pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc ? pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc ? pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc ? pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n ? v= 0) then pc ? pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n ? v= 1) then pc ? pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc ? pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc ? pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc ? pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc ? pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc ? pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc ? pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc ? pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc ? pc + k + 1 none 1/2 bit and bit-test instructions lsl rd logical shift left rd(n+1) ? rd(n), rd(0) ? 0 z,c,n,v,h 1 lsr rd logical shift right rd(n) ? rd(n+1), rd(7) ? 0 z,c,n,v 1 rol rd rotate left through carry rd(0) ? c,rd(n+1) ? rd(n),c ? rd(7) z,c,n,v,h 1 ror rd rotate right through carry rd(7) ? c,rd(n) ? rd(n+1),c ? rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) ? rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) ? rd(7..4),rd(7..4) ? rd(3..0) none 1 bset s flag set sreg(s) ? 1 sreg(s) 1 bclr s flag clear sreg(s) ? 0 sreg(s) 1 sbi a, b set bit in i/o register i/o(a, b) ? 1none1 151 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 cbi a, b clear bit in i/o register i/o(a, b) ? 0none1 bst rr, b bit store from register to t t ? rr(b) t 1 bld rd, b bit load from t to register rd(b) ? tnone1 sec set carry c ? 1c1 clc clear carry c ? 0 c 1 sen set negative flag n ? 1n1 cln clear negative flag n ? 0 n 1 sez set zero flag z ? 1z1 clz clear zero flag z ? 0 z 1 sei global interrupt enable i ? 1i1 cli global interrupt disable i ?? 0 i 1 ses set signed test flag s ? 1s1 cls clear signed test flag s ? 0 s 1 sev set two?s complement overflow. v ? 1v1 clv clear two?s complement overflow v ? 0 v 1 set set t in sreg t ? 1t1 clt clear t in sreg t ? 0 t 1 seh set half carry flag in sreg h ? 1h1 clh clear half carry flag in sreg h ? 0 h 1 data transfer instructions mov rd, rr copy register rd ? rr none 1 ldi rd, k load immediate rd ? knone1 ld rd, x load indirect rd ? (x) none 1/2 ld rd, x+ load indirect and post-increment rd ? (x), x ? x + 1 none 2 ld rd, - x load indirect and pre-decrement x ? x - 1, rd ? (x) none 2/3 ld rd, y load indirect rd ? (y) none 1/2 ld rd, y+ load indirect and post-increment rd ? (y), y ? y + 1 none 2 ld rd, - y load indirect and pre-decrement y ? y - 1, rd ? (y) none 2/3 ld rd, z load indirect rd ? (z) none 1/2 ld rd, z+ load indirect and post-increment rd ? (z), z ? z+1 none 2 ld rd, -z load indirect and pre-decrement z ? z - 1, rd ? (z) none 2/3 lds rd, k store direct from sram rd ??? k) none 1 st x, rr store indirect (x) ?? rr none 1 st x+, rr store indirect and post-increment (x) ?? rr, x ? x + 1 none 1 st - x, rr store indirect and pre-decrement x ? x - 1, (x) ? rr none 2 st y, rr store indirect (y) ? rr none 1 st y+, rr store indirect and post-increment (y) ? rr, y ? y + 1 none 1 st - y, rr store indirect and pre-decrement y ? y - 1, (y) ? rr none 2 st z, rr store indirect (z) ? rr none 1 st z+, rr store indirect and post-increment. (z) ? rr, z ? z + 1 none 1 st -z, rr store indirect and pre-decrement z ? z - 1, (z) ? rr none 2 sts k, rr store direct to sram (k) ? rr none 1 in rd, a in from i/o location rd ? i/o (a) none 1 out a, rr out to i/o location i/o (a) ? rr none 1 push rr push register on stack stack ? rr none 2 pop rd pop register from stack rd ? stack none 2 mcu control instructions break break (see specific descr. for break) none 1 nop no operation none 1 sleep sleep (see specific descr. for sleep) none 1 wdr watchdog reset (see specific descr. for wdr) none 1 mnemonics operands description operation flags #clocks 152 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 20. ordering information notes: 1. for speed vs. supply voltage, see section 16.3 ?speed? on page 116 . 2. all packages are pb-free, halide-free and fully green and they co mply with the european directive for restriction of hazard- ous substances (rohs). nipdau finish. 3. tape and reel. 4. can also be supplied in wafer form. contact your local atmel sales office for ordering information and minimum quantities. 5. top/bottomside markings: ? top: t4 x , where x = die revision ?bottom: z h zzz or z 8 zzz, where h = (-40 ? c to 85 ? c), and 8 = (-40 ? c to 125 ? c) 6. for typical and electrical characteristics for this device pl ease consult appendix a, attiny 4/5/9/10 specific ation at 125c. 20.1 attiny4 supply voltage speed (1) temperature package (2) ordering code (3) 1.8 ? 5.5v 12 mhz industrial (-40 ? c to 85 ? c) (4) 6st1 attiny4-tshr (5) 8ma4 attiny4-mahr (6) 10 mhz extended (-40 ? c to 125 ? c) (6) 6st1 attiny4-ts8r (5) package type 6st1 6-lead, 2.90 x 1.60 mm plastic small outline package (sot23) 8ma4 8-pad, 2 x 2 x 0.6 mm plastic ultra thin dual flat no lead (udfn) 153 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 notes: 1. for speed vs. supply voltage, see section 16.3 ?speed? on page 116 . 2. all packages are pb-free, halide-free and fully green and they co mply with the european directive for restriction of hazard- ous substances (rohs). nipdau finish. 3. tape and reel. 4. can also be supplied in wafer form. contact your local atmel sales office for ordering information and minimum quantities. 5. top/bottomside markings: ? top: t5 x , where x = die revision ?bottom: z h zzz or z 8 zzz, where h = (-40 ? c to 85 ? c), and 8 = (-40 ? c to 125 ? c) 6. for typical and electrical characteristics for this device pl ease consult appendix a, attiny 4/5/9/10 specific ation at 125c. 20.2 attiny5 supply voltage speed (1) temperature package (2) ordering code (3) 1.8 ? 5.5v 12 mhz industrial (-40 ? c to 85 ? c) (4) 6st1 attiny5-tshr (5) 8ma4 attiny5-mahr (6) 10 mhz extended (-40 ? c to 125 ? c) (6) 6st1 attiny5-ts8r (5) package type 6st1 6-lead, 2.90 x 1.60 mm plastic small outline package (sot23) 8ma4 8-pad, 2 x 2 x 0.6 mm plastic ultra thin dual flat no lead (udfn) 154 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 notes: 1. for speed vs. supply voltage, see section 16.3 ?speed? on page 116 . 2. all packages are pb-free, halide-free and fully green and they co mply with the european directive for restriction of hazard- ous substances (rohs). nipdau finish. 3. tape and reel. 4. can also be supplied in wafer form. contact your local atmel sales office for ordering information and minimum quantities. 5. top/bottomside markings: ? top: t9 x , where x = die revision ?bottom: z h zzz or z 8 zzz, where h = (-40 ? c to 85 ? c), and 8 = (-40 ? c to 125 ? c) 6. for typical and electrical characteristics for this device pl ease consult appendix a, attiny 4/5/9/10 specific ation at 125c. 20.3 attiny9 supply voltage speed (1) temperature package (2) ordering code (3) 1.8 ? 5.5v 12 mhz industrial (-40 ? c to 85 ? c) (4) 6st1 attiny9-tshr (5) 8ma4 attiny9-mahr (6) 10 mhz extended (-40 ? c to 125 ? c) (6) 6st1 attiny9-ts8r (5) package type 6st1 6-lead, 2.90 x 1.60 mm plastic small outline package (sot23) 8ma4 8-pad, 2 x 2 x 0.6 mm plastic ultra thin dual flat no lead (udfn) 155 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 notes: 1. for speed vs. supply voltage, see section 16.3 ?speed? on page 116 . 2. all packages are pb-free, halide-free and fully green and they co mply with the european directive for restriction of hazard- ous substances (rohs). nipdau finish. 3. tape and reel. 4. can also be supplied in wafer form. contact your local atmel sales office for ordering information and minimum quantities. 5. top/bottomside markings: ? top: t10 x , where x = die revision ?bottom: z h zzz or z 8 zzz, where h = (-40 ? c to 85 ? c), and 8 = (-40 ? c to 125 ? c) 6. for typical and electrical characteristics for this device pl ease consult appendix a, attiny 4/5/9/10 specific ation at 125c. 20.4 attiny10 supply voltage speed (1) temperature package (2) ordering code (3) 1.8 ? 5.5v 12 mhz industrial (-40 ? c to 85 ? c) (4) 6st1 attiny10-tshr (5) 8ma4 attiny10-mahr (6) 10 mhz extended (-40 ? c to 125 ? c) (6) 6st1 attiny10-ts8r (5) package type 6st1 6-lead, 2.90 x 1.60 mm plastic small outline package (sot23) 8ma4 8-pad, 2 x 2 x 0.6 mm plastic ultra thin dual flat no lead (udfn) 156 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 21. packaging information 21.1 6st1 title drawing no. gpc rev. package drawing contact: packagedrawings@atmel.com 6st1 taq a 6 s t1, 6-lead, 2.90 x 1.60 mm plastic small outline package (sot23) max note s ymbol min nom common dimen s ion s (unit of measure = mm) a ? ? 1.45 a1 0 ? 0.15 a2 0.90 ? 1.30 d 2.80 2.90 3.00 2 e 2.60 2.80 3.00 e1 1.50 1.60 1.75 l 0.30 0.45 0.55 e 0.95 bsc b 0.30 ? 0.50 3 c 0.09 ? 0.20 0 ? 8 notes: 1. this package is compliant with jedec specification mo-178 variation ab 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrustion or gate burrs shall not exceed 0.25 mm per end. 3. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm 4. die is facing down after trim/form. 6/30/08 s ide view e e1 d e a2 a a1 c c 0.10 0.25 l o a2 a a1 c c 0.10 a a see view b c seating plane seating plane seating plane c b pin #1 id 1 6 2 3 5 4 top view view b view a-a 157 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 21.2 8ma4 title drawing no. gpc rev. package drawing contact: packagedrawings@atmel.com 8ma4 yag a 8pad, 2x2x0.6 mm body, 0.5 mm pitch, 0.9x1.5 mm exposed pad, s aw singulated thermally enhanced plastic ultra thin dual flat no lead package (udfn/u s on) 12/17/09 common dimen s ion s (unit of measure = mm) s ymbol min nom max note a ? ? 0.60 a1 0.00 ? 0.05 b 0.20 ? 0.30 d 1.95 2.00 2.05 d2 1.40 1.50 1.60 e 1.95 2.00 2.05 e2 0.80 0.90 1.00 e ? 0.50 ? l 0.20 0.30 0.40 k 0.20 ? ? top view bottom view note: 1. all dimensions are in mm. angles in degrees. 2. coplanarity applies to the exposed pad as well as the terminals coplanarity shall not exceed 0.05 mm. 3. warpage shall not exceed 0.05 mm. 4. refer jedec mo-236/mo-252 pin 1 id e d d2 1 2 3 4 8 7 6 5 e2 b 1 4 8 5 e k l 0.05 s ide view a1 a c c 0.05 c 8x c0.2 158 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 22. errata the revision letters in this sect ion refer to the revision of the corresponding attiny4/5/9/10 device. 22.1 attiny4 22.1.1 rev. e ? programming lock bits 1. programming lock bits programming lock bits to a lock mode equal or lower than the current causes one word of flash to be cor- rupted. the location of the corruption is random. problem fix / workaround when programming lock bits, make sure lock mode is not set to presen t, or lower levels. 22.1.2 rev. d ? esd hbm (esd stm 5.1) level 1000v ? programming lock bits 1. esd hbm (esd stm 5.1) level 1000v the device meets esd hbm (esd stm 5.1) level 1000v. problem fix / workaround always use proper esd protection measures (class 1c ) when handling integrated circuits before and during assembly. 2. programming lock bits programming lock bits to a lock mode equal or lower than the current causes one word of flash to be cor- rupted. the location of the corruption is random. problem fix / workaround when programming lock bits, make sure lock mode is not set to presen t, or lower levels. 22.1.3 rev. a ? c not sampled. 159 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 22.2 attiny5 22.2.1 rev. e ? programming lock bits 1. programming lock bits programming lock bits to a lock mode equal or lower than the current causes one word of flash to be cor- rupted. the location of the corruption is random. problem fix / workaround when programming lock bits, make sure lock mode is not set to presen t, or lower levels. 22.2.2 rev. d ? esd hbm (esd stm 5.1) level 1000v ? programming lock bits 1. esd hbm (esd stm 5.1) level 1000v the device meets esd hbm (esd stm 5.1) level 1000v. problem fix / workaround always use proper esd protection measures (class 1c ) when handling integrated circuits before and during assembly. 2. programming lock bits programming lock bits to a lock mode equal or lower than the current causes one word of flash to be cor- rupted. the location of the corruption is random. problem fix / workaround when programming lock bits, make sure lock mode is not set to presen t, or lower levels. 22.2.3 rev. a ? c not sampled. 160 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 22.3 attiny9 22.3.1 rev. e ? programming lock bits 1. programming lock bits programming lock bits to a lock mode equal or lower than the current causes one word of flash to be cor- rupted. the location of the corruption is random. problem fix / workaround when programming lock bits, make sure lock mode is not set to presen t, or lower levels. 22.3.2 rev. d ? esd hbm (esd stm 5.1) level 1000v ? programming lock bits 1. esd hbm (esd stm 5.1) level 1000v the device meets esd hbm (esd stm 5.1) level 1000v. problem fix / workaround always use proper esd protection measures (class 1c ) when handling integrated circuits before and during assembly. 2. programming lock bits programming lock bits to a lock mode equal or lower than the current causes one word of flash to be cor- rupted. the location of the corruption is random. problem fix / workaround when programming lock bits, make sure lock mode is not set to presen t, or lower levels. 22.3.3 rev. a ? c not sampled. 161 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 22.4 attiny10 22.4.1 rev. e ? programming lock bits 1. programming lock bits programming lock bits to a lock mode equal or lower than the current causes one word of flash to be cor- rupted. the location of the corruption is random. problem fix / workaround when programming lock bits, make sure lock mode is not set to presen t, or lower levels. 22.4.2 rev. c ? d ? esd hbm (esd stm 5.1) level 1000v ? programming lock bits 1. esd hbm (esd stm 5.1) level 1000v the device meets esd hbm (esd stm 5.1) level 1000v. problem fix / workaround always use proper esd protection measures (class 1c ) when handling integrated circuits before and during assembly. 2. programming lock bits programming lock bits to a lock mode equal or lower than the current causes one word of flash to be cor- rupted. the location of the corruption is random. problem fix / workaround when programming lock bits, make sure lock mode is not set to presen t, or lower levels. 22.4.3 rev. a ? b not sampled. 162 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 23. datasheet revision history 23.1 rev. 8127f ? 02/13 1. updated: ? ordering information on page 152 , page 153 , page 154 , and page 155 23.2 rev. 8127e ? 11/11 1. updated: ? device status from preliminary to final ? ordering information on page 152 , page 153 , page 154 , and page 155 23.3 rev. 8127d ? 02/10 1. added udfn package in ?features? on page 1 , ?pin configurations? on page 2 , ?ordering information? on page 152 , and in ?packaging information? on page 156 2. updated figure 8-2 and figure 8-3 in section 8.2.1 ?power-on reset? on page 27 3. updated section 8.2.3 ?external reset? on page 29 4. updated figures 17-36 and 17-51 in ?typical characteristics? 5. updated notes in section 20. ?ordering information? on pages 152 - 155 6. added device rev. e in section 22. ?errata? on page 158 23.4 rev. 8127c ? 10/09 1. updated values and notes: ? table 16-1 in section 16.2 ?dc characteristics? on page 115 ? table 16-3 in section 16.4 ?clock characteristics? on page 117 ? table 16-6 in section 16.5.2 ?vcc level monitor? on page 118 ? table 16-9 in section 16.8 ?serial programming characteristics? on page 120 2. updated figure 16-1 in section 16.3 ?speed? on page 116 3. added typical characteristics figure 17-36 in section 17.8 ?analog comparator offset? on page 139 . also, updated some other plot s in typical characteristics. 4. added topside and bottomside marking notes in section 20. ?ordering information? on page 152 , up to page 155 5. added esd errata, see section 22. ?errata? on page 158 6. added lock bits re-programming errata, see section 22. ?errata? on page 158 23.5 rev. 8127b ? 08/09 1. updated document template 2. expanded document to also cover dev ices attiny4, attiny5 and attiny9 3. added section: ? ?comparison of attiny4, attiny5, attiny9 and attiny10? on page 4 4. updated sections: ? ?adc clock ? clkadc? on page 18 ? ?starting from idle / adc noise reduction / standby mode? on page 20 ? ?adc noise reduction mode? on page 24 ? ?analog to digital converter? on page 25 163 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 ? ?smcr ? sleep mode control register? on page 25 ? ?prr ? power reduction register? on page 26 ? ?alternate functions of port b? on page 48 ? ?overview? on page 82 ? ?physical layer of tiny programming interface? on page 95 ? ?overview? on page 106 ? ?adc characteristics (attiny5/10, only)? on page 119 ? ?supply current of i/o modules? on page 121 ? ?register summary? on page 148 ? ?ordering information? on page 152 5. added figure: ? ?using an external programmer for in-system programming via tpi? on page 96 6. updated figure: ? ?data memory map (byte addressing)? on page 15 7. added table: ? ?number of words and pages in the flash (attiny4/5)? on page 108 8. updated tables: ? ?active clock domains and wake-up sources in different sleep modes? on page 23 ? ?reset and interrupt vectors? on page 35 ? ?number of words and pages in the flash (attiny9/10)? on page 107 ? ?signature codes? on page 109 23.6 rev. 8127a ? 04/09 1. initial revision 164 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 1 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 table of contents features .............. ................. ................ .............. .............. .............. ............ 1 1 pin configurations .......... ................. ................ .............. .............. ............ 2 1.1 pin description ............ ......................................................................................2 2 overview ................. .............. .............. .............. .............. .............. ............ 3 2.1 comparison of attiny4, attiny5, attiny9 and attiny10 ....................................4 3 general information .... ................ ................ ................. ................ ............ 5 3.1 resources .........................................................................................................5 3.2 code examples .................................................................................................5 3.3 capacitive touch sensing .................................................................................5 3.4 data retention ...................................................................................................5 4cpu core ................. .............. .............. .............. .............. .............. ............ 6 4.1 architectural overview .......................................................................................6 4.2 alu ? arithmetic logic unit ...............................................................................7 4.3 status register ..................................................................................................7 4.4 general purpose register file ..........................................................................7 4.5 stack pointer .....................................................................................................9 4.6 instruction execution timing .............................................................................9 4.7 reset and interrupt handling ...........................................................................10 4.8 register description ........................................................................................11 5 memories ............... .............. .............. .............. .............. .............. ............ 14 5.1 in-system re-programmable flash prog ram memory ....................................14 5.2 data memory ...................................................................................................14 5.3 i/o memory ......................................................................................................16 6 clock system ................... ................. .............. .............. .............. ............ 17 6.1 clock subsystems ...........................................................................................17 6.2 clock sources .................................................................................................18 6.3 system clock prescaler ..................................................................................19 6.4 starting ............................................................................................................20 6.5 register description ........................................................................................21 7 power management and sleep modes .... ................ ................. ............ 23 7.1 sleep modes ....................................................................................................23 7.2 power reduction register ...............................................................................24 7.3 minimizing power consumption ......................................................................24 2 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 7.4 register description ........................................................................................25 8 system control and r eset ................... .............. .............. ............ .......... 27 8.1 resetting the avr ...........................................................................................27 8.2 reset sources .................................................................................................27 8.3 watchdog timer ..............................................................................................30 8.4 register description ........................................................................................32 9 interrupts ............... .............. .............. .............. .............. .............. ............ 35 9.1 interrupt vectors ..............................................................................................35 9.2 external interrupts ...........................................................................................36 9.3 register description ........................................................................................37 10 i/o ports ......... ................ ................ ................. .............. .............. ............ 40 10.1 overview ..........................................................................................................40 10.2 ports as general digital i/o .............................................................................41 10.3 alternate port functions ..................................................................................45 10.4 register description ........................................................................................50 11 16-bit timer/counter0 ........ .............. .............. .............. .............. ............ 52 11.1 features ..........................................................................................................52 11.2 overview ..........................................................................................................52 11.3 clock sources .................................................................................................54 11.4 counter unit ....................................................................................................55 11.5 input capture unit ...........................................................................................56 11.6 output compare units .....................................................................................58 11.7 compare match output unit ............................................................................60 11.8 modes of operation .........................................................................................61 11.9 timer/counter timing dia grams ......................................................................69 11.10 accessing 16-bit registers ..............................................................................70 11.11 register description ........................................................................................72 12 analog comparator ............ .............. .............. .............. .............. ............ 80 12.1 register description ........................................................................................80 13 analog to digital converter ................. .............. .............. ............ .......... 82 13.1 features ..........................................................................................................82 13.2 overview ..........................................................................................................82 13.3 operation .........................................................................................................82 13.4 starting a conversion ......................................................................................83 13.5 prescaling and conversion timing ..................................................................84 3 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 13.6 changing channel ...........................................................................................87 13.7 adc noise canceler .......................................................................................87 13.8 analog input circuitry ......................................................................................88 13.9 noise canceling techniques ...........................................................................88 13.10 adc accuracy definitions ...............................................................................89 13.11 adc conversion result ...................................................................................91 13.12 register description ........................................................................................92 14 programming interface .......... ................. ................ ................. .............. 95 14.1 features ..........................................................................................................95 14.2 overview ..........................................................................................................95 14.3 physical layer of tiny programming interface ................................................95 14.4 access layer of tiny programming interface ..................................................99 14.5 instruction set ................................................................................................100 14.6 accessing the non-volat ile memory controller .............................................103 14.7 control and status space register de scriptions ...........................................103 15 memory programming ........... ................. ................ ................. ............ 106 15.1 features ........................................................................................................106 15.2 overview ........................................................................................................106 15.3 non-volatile memories ..................................................................................106 15.4 accessing the nvm .......................................................................................109 15.5 self programming ..........................................................................................112 15.6 external programming ...................................................................................112 15.7 register description ......................................................................................114 16 electrical characteristics .. .............. .............. .............. .............. .......... 115 16.1 absolute maximum ratings* .........................................................................115 16.2 dc characteristics .........................................................................................115 16.3 speed ............................................................................................................116 16.4 clock characteristics .....................................................................................117 16.5 system and reset characteristics ................................................................118 16.6 analog comparator characteristics ...............................................................119 16.7 adc characteristics (attiny5/10, only ) .........................................................119 16.8 serial programming characteristics ... ...........................................................120 17 typical characteristics ...... .............. .............. .............. .............. .......... 121 17.1 supply current of i/o modules ......................................................................121 17.2 active supply current ....................................................................................122 4 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 17.3 idle supply current ........................................................................................125 17.4 power-down supply curr ent ..........................................................................127 17.5 pin pull-up .....................................................................................................128 17.6 pin driver strength ........................................................................................131 17.7 pin threshold and hysteresis ........................................................................135 17.8 analog comparator offset .............................................................................139 17.9 internal oscillator speed ...............................................................................140 17.10 vlm thresholds ............................................................................................142 17.11 current consumption of peripheral units ......................................................144 17.12 current consumption in reset and re set pulsewidth ...................................147 18 register summary .............. .............. .............. .............. .............. .......... 148 19 instruction set summary ..... .............. .............. .............. .............. ........ 150 20 ordering information ........... .............. .............. .............. .............. ........ 152 20.1 attiny4 ..........................................................................................................152 20.2 attiny5 ..........................................................................................................153 20.3 attiny9 ..........................................................................................................154 20.4 attiny10 ........................................................................................................155 21 packaging information ....... .............. .............. .............. .............. .......... 156 21.1 6st1 ..............................................................................................................156 21.2 8ma4 .............................................................................................................157 22 errata ........... ................. ................ ................ ................. .............. .......... 158 22.1 attiny4 ..........................................................................................................158 22.2 attiny5 ..........................................................................................................159 22.3 attiny9 ..........................................................................................................160 22.4 attiny10 ........................................................................................................161 23 datasheet revision history .. ............. .............. .............. .............. ........ 162 23.1 rev. 8127f ? 02/13 .......................................................................................162 23.2 rev. 8127e ? 11/11 .......................................................................................162 23.3 rev. 8127d ? 02/10 .......................................................................................162 23.4 rev. 8127c ? 10/09 .......................................................................................162 23.5 rev. 8127b ? 08/09 .......................................................................................162 23.6 rev. 8127a ? 04/09 .......................................................................................163 table of contents ...... ................. ................ ................ ................. .............. 1 features1 1 table of contents1 4 5 attiny4/5/9/10 [datasheet] 8127f?avr?02/2013 atmel corporation 1600 technology drive san jose, ca 95110 usa tel: (+1) (408) 441-0311 fax: (+1) (408) 487-2600 www.atmel.com atmel asia limited unit 01-5 & 16, 19f bea tower, millennium city 5 418 kwun tong roa kwun tong, kowloon hong kong tel: (+852) 2245-6100 fax: (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel: (+49) 89-31970-0 fax: (+49) 89-3194621 atmel japan g.k. 16f shin-osaki kangyo bldg 1-6-4 osaki, shinagawa-ku tokyo 141-0032 japan tel: (+81) (3) 6417-0300 fax: (+81) (3) 6417-0370 ? 2013 atmel corporation. all rights reserved. / rev.: 8127f?avr?02/2013 disclaimer: the information in this document is provided in co nnection with atmel products. no lic ense, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. exc ept as set forth in the atmel terms and conditions of sales locat ed on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not li mited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any d irect, indirect, consequential, punitive, special or incide ntal damages (including, without limitation, damages for loss and profits, business i nterruption, or loss of information) arising out of the us e or inability to use this document, even if at mel has been advised of the possibility of suc h damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the ri ght to make changes to specifications and products descriptions at any time without notice. atmel does not make any commitment to update th e information contained herein. un less specifically provided oth erwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel products are not intended, authorized, or warranted for use as components in applications intend ed to support or sustain life. atmel ? , atmel logo and combinations thereof, enabling unlimited possibilities ? , avr ? , tinyavr ? and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others. |
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